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ICS87974AYLF PDF预览

ICS87974AYLF

更新时间: 2024-09-30 19:47:51
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
12页 123K
描述
PLL Based Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52

ICS87974AYLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP,针数:52
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.09输入调节:MUX
JESD-30 代码:S-PQFP-G52JESD-609代码:e3
长度:10 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:52实输出次数:15
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.35 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

ICS87974AYLF 数据手册

 浏览型号ICS87974AYLF的Datasheet PDF文件第2页浏览型号ICS87974AYLF的Datasheet PDF文件第3页浏览型号ICS87974AYLF的Datasheet PDF文件第4页浏览型号ICS87974AYLF的Datasheet PDF文件第5页浏览型号ICS87974AYLF的Datasheet PDF文件第6页浏览型号ICS87974AYLF的Datasheet PDF文件第7页 
PRELIMINARY  
ICS87974  
LOW SKEW, 1-TO-15,  
LVCMOS CLOCK GENERATOR  
Integrated  
Circuit  
Systems, Incꢀ  
GENERAL DESCRIPTION  
FEATURES  
Fully integrated PLL  
The ICS87974 is a low skew, low jitter 1-to-15  
LVCMOS clock generator/zero delay buffer and is  
HiPerClockS™  
15 single ended 3.3V LVCMOS outputs  
a member of the HiPerClockS family of high per-  
formance clock solutions from ICS. The device has  
a fully integrated PLL and three banks whose di-  
Selectable CLK0 or CLK1 inputs for  
redundant clock applications  
vider ratios can be independently controlled, providing output  
frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In addition,  
the external feedback connection provides for a wide selection  
of output-to-input frequency ratios. The CLK0 and CLK1 pins  
allow for redundant clocking on the input and dynamically switch-  
ing the PLL between two clock sources. The ICS87974 is pin  
for pin compatible with the MPC974.  
Maximum output frequency: 125MHz  
VCO range: 200MHz - 700MHz  
External feedback for ”zero delay” clock regeneration  
Cycle-to-cycle jitter: ±100ps (typical)  
Output skew: 350ps (maximum)  
Guaranteed low jitter and output skew characteristics make the  
ICS87974 ideal for those applications demanding well defined  
performance and repeatability.  
Bank skew: 50ps (typical)  
PLL reference zero delay: -250ps to 100ps  
3.3V operating supply  
Pin compatible with the MPC974  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
PIN ASSIGNMENT  
52 51 50 49 48 47 46 45 44 43 42 41 40  
GND  
nMR  
1
GND  
QB1  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
2
CLK_EN  
SELB  
3
VDDOB  
QB2  
4
SELC  
PLL_SEL  
SELA  
5
GND  
QB3  
6
7
VDDOB  
QB4  
ICS87974  
CLK_SEL  
CLK0  
8
9
FB_IN  
GND  
QFB  
CLK1  
10  
11  
12  
13  
nc  
VDD  
VDDOFB  
nc  
VDDA  
14 15 16 17 18 19 20 21 22 23 24 25 26  
52-Lead LQFP  
10mm x 10mm x 1.4mm package body  
Y package  
Top View  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
87974AY  
www.icst.com/products/hiperclocks.html  
REV. B FEBRUARY 13, 2002  
1

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