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ICS650-21 PDF预览

ICS650-21

更新时间: 2022-12-01 12:20:15
品牌 Logo 应用领域
矽成 - ICSI 时钟
页数 文件大小 规格书
4页 66K
描述
System Peripheral Clock Source

ICS650-21 数据手册

 浏览型号ICS650-21的Datasheet PDF文件第1页浏览型号ICS650-21的Datasheet PDF文件第3页浏览型号ICS650-21的Datasheet PDF文件第4页 
PRELIMINARY INFORMATION  
ICS650-21  
System Peripheral Clock Source  
Pin Assignment  
Processor Clock (MHz)  
PSEL1 PSEL0  
PCLK1  
25.00  
37.5  
66.66  
40.00  
33.3334  
20.00  
20.00  
20.00  
PCLK2,3  
50.00  
75.00  
133.33  
80.00  
66.6667  
40.00  
PSEL1  
USEL  
1
2
3
4
5
6
7
20  
0
0
0
0
M
1
19 PSEL0  
18 PCLK2  
X2  
X1/ICLK  
VDD  
M
M
M
1
0
M
1
PCLK3  
VDD  
17  
16  
0
33.3334  
66.6667  
VDD  
1
M
1
1
50  
100  
GND  
15  
14  
13  
12  
11  
ASEL  
USB Clock (MHz)  
USEL  
UCLK  
Audio Clock (MHz)  
GND  
ASEL  
ACLK  
49.152  
24.576  
14.318  
UCLK  
20M  
ACLK  
25M  
8
OFF/14.318M  
PCLK1  
OE  
0
M
1
0
M
1
12  
9
24  
48  
10  
0 = connect directly to ground, 1 = connect directly  
to VDD, M=leave unconnected (floating)  
20 pin (150 mil) SSOP  
Pin Descriptions  
Pin #  
Name  
USEL  
X2  
X1/ICLK  
VDD  
VDD  
GND  
UCLK  
20M  
ACLK  
25M  
Type Description  
1
2
3
4
5
6
7
I
XO  
XI  
P
P
P
UCLK Select pin. Determines frequency of USB clock per table above.  
Crystal connection. Connect to parallel mode 25 MHz crystal. Leave open for clock.  
Crystal connection. Connect to parallel mode 25 MHz crystal, or clock.  
Connect to VDD. Must be same value as other VDD. Decouple with pin 6.  
Connect to VDD. Must be same value as other VDD.  
Connect to ground.  
O
O
O
O
I
USB clock output per table above.  
Fixed 20 MHz output for Ethernet.  
AC97 Audio clock output per table above.  
Fixed 25 MHz reference output for Fast Ethernet.  
Output Enable. Tri-states all outputs when low.  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
OE  
PCLK1  
OFF/14.318M  
GND  
O
O
P
PCLK output number 1 per table above.  
14.31818 MHz clock output only when ASEL=VDD.  
Connect to ground.  
ASEL  
VDD  
PCLK3  
PCLK2  
PSEL0  
PSEL1  
I
P
O
O
I
ACLK Select pin. Determines frequency of Audio clock per table above.  
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.  
PCLK output number 3 per table above.  
PCLK output number 2 per table above.  
Processor Select pin #0. Determines frequencies on PCLKs 1-3 per table above.  
Processor Select pin #1. Determines frequencies on PCLKs 1-3 per table above.  
I
Key: I = Input; XO/XI = crystal connections; O = output; P = power supply connection  
MDS 650-21 A  
2
Revision 010301  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com  

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