Datasheet > ICS650-27

ICS650-27

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
6页	153K
描述
Networking Clock Source

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ICS650-27 数据手册

ICS650-27

Networking Clock Source

Description

Features

The ICS650-27 is a low cost, low jitter, high

• Packaged in 20-pin (150 mil) SSOP (QSOP)

• Available in Pb (lead) free package

performance clock synthesizer for networking

applications. Using analog Phase-Locked Loop (PLL)

techniques, the device accepts a 12.5 MHz or 25 MHz

clock or fundamental mode crystal input to produce

multiple output clocks for networking chips, PCI

devices, SDRAM, and ASICs. The ICS650-27 outputs

all have zero ppm synthesis error.

• 12.5 MHz or 25 MHz fundamental crystal or clock

input

• Six output clocks with selectable frequencies

• SDRAM frequencies of 67, 83, 100, and 133 MHz

• Buffered crystal reference output

• Zero ppm synthesis error in all clocks

• Ideal for PMC-Sierra’s ATM switch chips

The ICS650-27 is pin compatible and functionally

equivalent to the ICS650-07. It is a performance

upgrade and is recommended for all new 3.3V

designs.

• Full CMOS output swing with 25 mA output drive

capability at TTL levels

• Advanced, low-power, sub-micron CMOS process

• Operating voltage of 3.3 V

See the MK74CB214, ICS551, and ICS552-01 for

non-PLL buffer devices which produce multiple

low-skew copies of these output clocks.

• Industrial temperature only

See the ICS570, ICS9112-16/17/18 for zero delay

buffers that can synchronize outputs and other needed

clocks.

Block Diagram

VDD

CLKA1

ACS1:0

CLKA2

CLKB1

Clock

BCS1:0

Synthesis

and Control

CLKB2

CCS

Circuitry

CLKC1

CLKC2

X1/ICLK

Clock

Buffer/

Crystal

Oscillator

25 or 12.5 MHz

cyrstal or clock

REFOUT

OE (all outputs)

GND

MDS 650-27 D

Revision 070505

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

12 3 4 5 6

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