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ICM7610 PDF预览

ICM7610

更新时间： 2024-01-03 13:04:49
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ICMIC /
页数 文件大小 规格书
12页 222K
描述
12/10/8-Bit Low Power Voltage Output Quad DACs With Parallel Interface

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ICM7610 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Contact Manufacturer零件包装代码：TSSOP
包装说明：TSSOP, TSSOP24,.25针数：24
Reach Compliance Code：unknown风险等级：5.45
最大模拟输出电压：5.5 V最小模拟输出电压：
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：PARALLEL, WORDJESD-30 代码：R-PDSO-G24
长度：6.5 mm最大线性误差 (EL)：0.293%
位数：10功能数量：1
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3/5 V
认证状态：Not Qualified座面最大高度：1.2 mm
标称安定时间 (tstl)：8 µs子类别：Other Converters
最大压摆率：0.7 mA标称供电电压：3.6 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

ICM7610 数据手册

 浏览型号ICM7610的Datasheet PDF文件第4页浏览型号ICM7610的Datasheet PDF文件第5页浏览型号ICM7610的Datasheet PDF文件第6页浏览型号ICM7610的Datasheet PDF文件第8页浏览型号ICM7610的Datasheet PDF文件第9页浏览型号ICM7610的Datasheet PDF文件第10页 
ICM7620/7610/7600  
LDAC  
WR  
A1  
X
0
A0  
X
0
LATCH STATE  
1
1
0
0
1
1
1
1
Input and DAC data latched  
0
1
0
0
0
0
Input Latch transparent – DAC A  
X
0
X
0
DAC Latch transparent – All DACs  
DAC latch of All DACs transparent and DAC A input latch transparent  
Input Latch transparent – DAC B  
0
1
1
0
Input Latch transparent – DAC C  
1
1
Input Latch transparent – DAC D  
Table 1. Address Table  
DETAILED DESCRIPTION  
The ICM7620 is a 12-bit voltage output Quad DAC. The ICM7610 is the 10-bit version of this family and the ICM7600 is the 8-bit  
version. These devices have a parallel interface and each DAC has a double buffered input. This family of DACs has a  
guaranteed monotonic behavior. The operating supply range is from 2.7V to 5.5V.  
Reference Input  
The reference input accepts positive DC and AC signals. The voltage at REFIN sets the full-scale output voltage of all the DACs.  
The reference input voltage range is from 0 to VDD-1.5V. The impedance at this pin is nominally about 40 K Ω. Each DACs output  
amplifier is configured in a gain of 2 configuration. This means that the full-scale output of each DAC will be 2x VREF. To determine  
the output voltage for any code, use the following equation.  
VOUT = 2 x (VREF x (D / (2n)))  
Where D is the numeric value of DAC’s decimal input code, VREF is the reference voltage and n is number of bits, i.e. 12 for  
ICM7620, 10 for ICM7610 and 8 for ICM7600.  
Output Buffer Amplifier  
The Quad DAC has 4 output amplifiers connected in a gain of 2 configuration. These amplifiers have a wide output voltage swing.  
The actual swing of the output amplifiers will be limited by offset error and gain error. See the Applications Information Section for  
a more detailed discussion.  
The output amplifier can drive a load of 2.0 K Ω to VDD or GND in parallel with a 500 pF load capacitance and has a full-scale  
typical settling time of 8 µs.  
Input Logic  
This quad DAC family uses a standard straight parallel interface where D0 is the LSB and D11 is the MSB for the ICM7620, D9 is  
the MSB for the ICM7610 and D7 is the MSB for the ICM7600. Each DAC has its own double buffered input with an input latch  
and a DAC latch. Each DAC will go the voltage output that corresponds to the digital data that is stored in its DAC latch.  
Input (active low), controls the input latch data and the  
The WR  
LDAC Input (active low) updates the DAC latches (Table 1).  
Please refer to the Timing Diagram for more detail. The address inputs (A1, A0) control DAC addressing (Table 1).  
Power-Down Mode  
These parts offer shutdown capability to the user by means of the SHDN pin. When this pin is forced high all the DACs power  
down and the REF input goes into high impedance state. The total current consumption will go down to below 10 µA in power  
down mode. The data is stored in the latches during power down and the DACs will power up in the previous state when SHDN is  
driven back to logic low.  
Power-On Reset  
There is a power-on reset on board that will clear the contents of all the latches to all 0s on power-up and the DAC voltage output  
will go to ground.  
7
Rev. A7  
ICmic reserves the right to change specifications without prior notice  
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