Datasheet > HY57V281620HCLT-8I

HY57V281620HCLT-8I

更新时间： 2024-02-10 18:11:27

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
11页	78K
描述
4 Banks x 2M x 16bits Synchronous DRAM

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中文翻译

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HY57V281620HC(L/S)T-I Series

4 Banks x 2M x 16bits Synchronous DRAM

DESCRIPTION

The Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which

require low power consumption and extended temperature range. HY57V281620HC(L/S)T is organized as 4banks of 2,097,152x16

HY57V281620HC(L/S)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are

synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input

and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated

by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of

read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by UDQM or LDQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V281620HCT-6I

HY57V281620HCT-7I

166MHz

143MHz

133MHz

125MHz

100MHz

166MHz

143MHz

133MHz

125MHz

100MHz

HY57V281620HCT-KI

HY57V281620HCT-HI

Normal

HY57V281620HCT-8I

HY57V281620HCT-PI

HY57V281620HCT-SI

4Banks x 2Mbits

x16

LVTTL

400mil 54pin TSOP II

HY57V281620HC(L/S)T-6I

HY57V281620HC(L/S)T-7I

HY57V281620HC(L/S)T-KI

HY57V281620HC(L/S)T-HI

HY57V281620HC(L/S)T-8I

HY57V281620HC(L/S)T-PI

HY57V281620HC(L/S)T-SI

Low power

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use

of circuits described. No patent licenses are implied.

Rev. 1.0/Mar. 02

12 3 4 5 6 7...11

中文翻译

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与HY57V281620HCLT-8I相关器件

型号	品牌	获取价格	描述	数据表
HY57V281620HCLT-H	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCLT-HI	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCLT-I	ETC	获取价格	8Mx16\|3.3V\|4K\|6\|SDR SDRAM - 128M
HY57V281620HCLT-K	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCLT-KI	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCLT-P	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCLTP-6	HYNIX	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE
HY57V281620HCLTP-7	HYNIX	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE
HY57V281620HCLTP-8	HYNIX	获取价格	Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE,
HY57V281620HCLTP-H	HYNIX	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE

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