HY57V281620HCLTP-K

更新时间： 2024-02-14 15:14:13

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
13页	97K
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中文翻译

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数据手册

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HY57V281620A

4 Banks x 2M x 16bits Synchronous DRAM

DESCRIPTION

The Hynix HY57V281620A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V281620A is organized as 4banks of 2,097,152x16

HY57V281620A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated

by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of

read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by UDQM or LDQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V281620AT-6

HY57V281620AT-7

HY57V281620AT-K

HY57V281620AT-H

HY57V281620AT-8

HY57V281620AT-P

HY57V281620AT-S

HY57V281620ALT-6

HY57V281620ALT-7

HY57V281620ALT-K

HY57V281620ALT-H

HY57V281620ALT-8

HY57V281620ALT-P

HY57V281620ALT-S

166MHz

143MHz

133MHz

125MHz

100MHz

166MHz

143MHz

133MHz

125MHz

100MHz

Normal

4Banks x 2Mbits

x16

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits de-

scribed. No patent licenses are implied.

Rev. 1.3/Aug. 01

12 3 4 5 6 7...13

中文翻译

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与HY57V281620HCLTP-K相关器件

型号	品牌	获取价格	描述	数据表
HY57V281620HCLTP-P	HYNIX	获取价格	Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE,
HY57V281620HCLTP-S	HYNIX	获取价格	Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE,
HY57V281620HCLT-S	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCLT-SI	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCST-6I	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCST-7I	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCST-8I	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCST-HI	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCST-KI	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCST-PI	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM

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