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HV4630DJ PDF预览

HV4630DJ

更新时间: 2024-01-13 19:31:28
品牌 Logo 应用领域
其他 - ETC 接口集成电路驱动
页数 文件大小 规格书
6页 39K
描述
Converter

HV4630DJ 技术参数

生命周期:Obsolete零件包装代码:DIE
包装说明:DIE,针数:41
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
数据输入模式:SERIAL显示模式:DOT MATRIX
接口集成电路类型:EL DISPLAY DRIVERJESD-30 代码:R-XUUC-N41
复用显示功能:NO标称负供电电压:-12 V
功能数量:1区段数:32
端子数量:41最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:DIE封装形状:RECTANGULAR
封装形式:UNCASED CHIP认证状态:Not Qualified
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:NO LEAD
端子位置:UPPER最小 fmax:8 MHz
Base Number Matches:1

HV4630DJ 数据手册

 浏览型号HV4630DJ的Datasheet PDF文件第2页浏览型号HV4630DJ的Datasheet PDF文件第3页浏览型号HV4630DJ的Datasheet PDF文件第4页浏览型号HV4630DJ的Datasheet PDF文件第5页浏览型号HV4630DJ的Datasheet PDF文件第6页 
HV4522/HV4530  
HV4622/HV4630  
32-Channel Serial To Parallel Converter  
with P-Channel Open Drain Outputs  
Ordering Information  
Package Options  
Recommended  
Device  
Operating  
VPP Max  
44 J-Lead Quad  
Ceramic Chip Carrier  
44 J-Lead Quad  
44 Quad Plastic  
Gullwing  
Die  
Plastic Chip Carrier  
HV4522PJ*  
HV4522  
HV4530  
HV4622  
HV4630  
-220  
-300  
-220  
-300  
HV4522DJ*  
HV4530DJ*  
HV4622DJ*  
HV4630DJ*  
HV4522PG*  
HV4530PG  
HV4622PG*  
HV4630PG  
HV4522X  
HV4530X  
HV4622X  
HV4630X  
HV4530PJ  
HV4622PJ*  
HV4630PJ  
* Not Recommended for New Design  
Features  
Processed with HVCMOS Technology  
General Description  
The HV45 and HV46 are low-voltage serial to high-voltage  
parallel converters with P-Channel open drain outputs. These  
devices have been designed for use as drivers for AC-electrolu-  
minescent displays. They can also be used in any application  
requiring multiple output high-voltage current source capabilities  
such as driving inkjet and electrostatic print heads, plasma  
panels, or vacuum fluorescent displays.  
Output voltages to -300V  
Source current minimum 60 mA  
Shift register speed 8 MHz  
Polarity and blanking inputs  
CMOS compatible inputs  
These devices consist of a 32-bit shift register, 32 data latches,  
and control logic to perform polarity and blanking functions. Data  
is shifted through the shift register on the logic high-to-low  
transition of the clock. The HV45 shifts in the counterclockwise  
direction when viewed from the top of the package and the HV46  
shifts in the clockwise direction. A data output buffer is provided  
for cascading devices. This output reflects the current status of  
the last bit of the shift register. The data in the shift register is  
latched when the latch enable pin is brought to logic high and then  
returned to ground. If the latch enable pin is held high, the latch  
becomes transparent and the shift register data is directly re-  
flected in the outputs.  
Forward and reverse shifting options  
44-lead plastic and ceramic surface mount packages  
Hi-Rel processing available  
12  
Can be used with the HV55 and HV56 to provide 300V  
push pull operation  
Absolute Maximum Ratings1  
Supply voltage, VDD  
+0.5V to -16V  
Off state output voltage  
HV4530/HV4630 +0.5V to -315V  
HV4522/ HV4622 +0.5V to -240V  
+0.5V to VDD - 0.3V  
For applications requiring active pull down as well as pull up, the  
HV45 and HV46 can be paired with the HV55 and HV56 devices,  
respectively.  
Logic input levels  
Ground current2  
1.5A  
Continuous total power dissipation3 Plastic  
Ceramic  
1200mW  
1500mW  
Operating temperature range  
Ceramic -55°C to +125°C  
Plastic -40°C to +85°C  
Storage temperature range  
-65°C to +150°C  
260°C  
Lead temperature 1.6mm (1/16 inch)  
from case for 10 seconds  
Notes:  
1. All voltages are referenced to VSS  
.
2. Duty cycle is limited by the total power dissipated in the package.  
3. For operation above 25°C ambient derate linearly to maximum operating  
temperature at 20mW/°C for plastic and at 15mW/°C for ceramic.  
12-23  

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