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HT32F12364

更新时间： 2024-03-03 10:10:20

品牌	Logo	应用领域
台湾合泰/盛群 - HOLTEK		/
页数	文件大小	规格书
48页	1174K
描述
32-bit Arm? Cortex?-M3 MCU

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HT32F12364 数据手册

32-Bit Arm^®Cortex^®-M3 MCU

HT32F12364

Features

Core

32-bit Arm^®Cortex^®-M3 processor core

▆

Up to 72 MHz operating frequency

Single-cycle multiplication and hardware division

Integrated Nested Vectored Interrupt Controller (NVIC)

24-bit SysTick timer

The Cortex -M3 processor is a general-purpose 32-bit processor core especially suitable for

products requiring high performance and low power consumption microcontrollers. It oﬀers many

special features such as a Thumb-2 instruction set, hardware divider, low latency interrupt respond

time, atomic bit-banding access and multiple buses for simultaneous accesses. The Cortex -M3

processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction

sets.

On-Chip Memory

▆

256 KB on-chip Flash memory for instruction/data and option storage

128 KB on-chip SRAM

Supports multiple booting modes

The Arm Cortex -M3 processor is structured using Harvard architecture which uses a separate

bus structure to fetch instructions and load/store data. The instruction code and data are both

located in the same memory address space but in diﬀerent address ranges. The maximum address

range of the Cortex -M3 is 4 GB due to its 32-bit bus address width. Additionally, a pre-deﬁned

memory map is provided by the Cortex -M3 processor to reduce the software complexity of

repeated implementation for diﬀerent device vendors. However, some regions are used by the Arm

Cortex -M3 system peripherals. Refer to the Arm Cortex -M3 Technical Reference Manual for

more information. Figure 2 in the Overview chapter shows the memory map of the HT32F12364

device, including Code, SRAM, peripheral and other pre-deﬁned regions.

Flash Memory Controller – FMC

▆

Flash accelerator for maximum eﬃciency

▆

32-bit word programming with In System Programming (ISP) and In Application Programming

(IAP)

▆

Flash protection capability to prevent illegal access

The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer

for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower

than the CPU, a wide access interface with a pre-fetch buﬀer and cache are provided for the Flash

Memory in order to reduce the CPU waiting time which will cause CPU instruction execution

delays. Flash Memory word programming/page erase functions are also provided.

Rev. 1.20

7 of 48

February 24, 2021

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