Datasheet > HSD32M64D8A-10

HSD32M64D8A-10

更新时间： 2024-01-23 14:16:12

品牌	Logo	应用领域
HANBIT		动态存储器
页数	文件大小	规格书
10页	80K
描述
DRAM

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HSD32M64D8A-10 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
Base Number Matches：	1

HSD32M64D8A-10 数据手册

HANBit

HSD32M64D8A

Synchronous DRAM Module 64Mbyte (8Mx72bit),DIMM based on

32Mx8, 4Banks, 8K Ref., 3.3V

Part No. HSD32M64D8A

GENERAL DESCRIPTION

The HSD32M64D8A is a 32M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists

of eight

CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy

substrate. Two 0.33uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The

HSD32M64D8A is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets.

Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high

bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC

power supply and all inputs and outputs are LVTTL-compatible.

FEATURES

• Part Identification

HSD32M64D8A-F/10L : 100MHz (CL=3)

HSD32M64D8A-F/10 : 100MHz (CL=2)

HSD32M64D8A-F/13 : 133MHz (CL=3)

HSD32M64D8A-F/12 : 125MHz (CL=3)

F means Auto & Self refresh with Low-Power (3.3V)

• Burst mode operation

• Auto & self refresh capability (8192 Cycles/64ms)

• LVTTL compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• MRS cycle with address key programs

- Latency (Access from column address)

- Burst length (1, 2, 4, 8 & Full page)

- Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock

• The used device is 8M x 8bit x 4Banks SDRAM

URL:www.hbe.co.kr

REV.1.0 (August.2002)

- 1 -

HANBit Electronics Co.,Ltd.

12 3 4 5 6 7...10

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