HS-81C55RH, HS-81C56RH
TM
Data Sheet
August 2000
File Number 3039.2
Radiation Hardened 256 x 8 CMOS RAM
Features
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
• Electrically Screened to SMD # 5962-96766
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened EPI-CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
8
- Transient Upset. . . . . . . . . . . . . . . . . .>1 x 10 rad(Si)/s
12
- Latch-Up Free. . . . . . . . . . . . . . . . . .>1 x 10 rad(Si)/s
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system.
The RAM portion is designed as 2048 static cells organized
as 256 x 8. A maximum post irradiation access time of
500ns allows the HS-81C55/56RH to be used with the
HS-80C85RH CPU without any wait states. The
HS-81C55RH requires an active low chip enable while the
HS-81C56RH requires an active high chip enable. These
chips are designed for operation utilizing a single 5V power
supply.
• Electrically Equivalent to Sandia SA 3001
• Pin Compatible with Intel 8155/56
• Bus Compatible with HS-80C85RH
• Single 5V Power Supply
• Low Standby Current . . . . . . . . . . . . . . . . . . . .200µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . . . . 2mA/MHz
• Completely Static Design
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
• Internal Address Latches
• Two Programmable 8-Bit I/O Ports
• One Programmable 6-Bit I/O Port
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96766. A “hot-link” is provided
on our homepage for downloading.
• Programmable 14-Bit Binary Counter/Timer
• Multiplexed Address and Data Bus
• Self Aligned Junction Isolated (SAJI) Process
http://www.intersil.com/spacedefense/space.asp
Ordering Information
o
o
• Military Temperature Range . . . . . . . . . . . -55 C to 125 C
INTERNAL
MKT. NUMBER
TEMP. RANGE
o
Functional Diagram
ORDERING NUMBER
5962R9676601QXC
5962R9676601QYC
5962R9676601VXC
5962R9676601VYC
5962R9676602QXC
5962R9676602QYC
5962R9676602VXC
5962R9676602VYC
( C)
HS1-81C55RH-8
HS9-81C55RH-8
HS1-81C55RH-Q
HS9-81C55RH-Q
HS1-81C56RH-8
HS9-81C56RH-8
HS1-81C56RH-Q
HS9-81C56RH-Q
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PORT A
IO/M
256 x 8
STATIC
RAM
8
PA0 - PA7
PB0 - PB7
PC0 - PC5
A
B
C
AD0 - AD7
CE OR CE†
ALE
PORT B
8
RD
PORT C
8
WR
RESET
TIMER
VDD (10V)
GND
TIMER CLK
TIMER OUT
† 81C55RH = CE
81C56RH = CE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
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