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HMS25632J2-10 PDF预览

HMS25632J2-10

更新时间: 2024-01-16 18:42:25
品牌 Logo 应用领域
HANBIT 静态存储器
页数 文件大小 规格书
6页 49K
描述
SRAM MODULE 1Mbyte (256K x 32-Bit), 5V, 68-Pin JLCC Design

HMS25632J2-10 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.8
Base Number Matches:1

HMS25632J2-10 数据手册

 浏览型号HMS25632J2-10的Datasheet PDF文件第1页浏览型号HMS25632J2-10的Datasheet PDF文件第2页浏览型号HMS25632J2-10的Datasheet PDF文件第3页浏览型号HMS25632J2-10的Datasheet PDF文件第5页浏览型号HMS25632J2-10的Datasheet PDF文件第6页 
HANBit  
HMS25632J2  
o
o
AC CHARACTERISTICS (0 C £ T  
£ 70 C ; Vcc = 5.0V ± 10%, unless otherwise specified)  
A
PARAMETER  
VALUE  
Input Pulse Level  
0 to 3V  
3ns  
Input Rise and Fall Time  
Input and Output Timing Reference Levels  
Output Load  
1.5V  
See below  
TEST CONDITIONS  
Output Load (B)  
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ  
+5.0V  
Output Load (A)  
VL=1.5V  
50W  
480W  
DOUT  
DOUT  
Z0=50W  
255W  
30pF  
5pF*  
READ CYCLE  
-10  
-12  
-15  
PARAMETER  
SYMBOL  
UNIT  
MIN  
10  
-
MAX  
MIN  
12  
-
MAX  
MIN  
15  
-
MAX  
Read Cycle Time  
tRC  
tAA  
-
10  
10  
5
5
-
-
12  
12  
6
6
-
-
15  
15  
7
7
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
tCO  
tOE  
tBA  
-
-
-
Output Enable to Valid Output  
/BS0 ~ /BS3 Access Time  
-
-
-
-
-
-
Chip Enable to Low-Z Output  
Output Enable to Low-Z Output  
/BS0 ~ /BS3 Enable to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
/BS0 ~ /BS3 Disable to High-Z Output  
Output Hold from address Change  
tLZ  
3
3
3
tOLZ  
tBHZ  
tHZ  
0
-
0
-
0
-
0
-
0
-
0
-
0
5
5
5
-
0
6
6
6
-
0
7
7
7
-
tOHZ  
tBHZ  
tOH  
0
0
0
0
0
0
Ns  
Ns  
3
3
3
URL: www.hbe.co.kr  
4
HANBit ElectronicsCo.,Ltd.  
Rev. 1.0 (September / 2002)  

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