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HMC960 PDF预览

HMC960

更新时间: 2023-12-20 18:45:04
品牌 Logo 应用领域
亚德诺 - ADI 放大器驱动驱动器
页数 文件大小 规格书
20页 1212K
描述
集成驱动器的DC - 100 MHz双通道数字可变增益放大器,采用SMT封装

HMC960 数据手册

 浏览型号HMC960的Datasheet PDF文件第14页浏览型号HMC960的Datasheet PDF文件第15页浏览型号HMC960的Datasheet PDF文件第16页浏览型号HMC960的Datasheet PDF文件第17页浏览型号HMC960的Datasheet PDF文件第18页浏览型号HMC960的Datasheet PDF文件第19页 
HMC960LP4E  
v01.1212  
DC - 100 MHz DUAL DigitAL  
VAriAbLe gAin AMpLifier wꢀꢁh DriVer  
[1][2]  
taꢇlꢆ 10. rꢆꢃ 03h - gaꢀꢂ Coꢂꢁꢄol rꢆꢃꢀsꢁꢆꢄ WHen USing dꢆcodꢆ loꢃꢀc  
Bit  
Name  
Width  
Default  
Description  
Reg 02h[5]=1 and Reg 02h[6]=0  
(i.e. SPI gain control & gain decode enabled)  
gain[6:0] defines teh VGA channel I and Q gain of 0-40dB as follows...  
0000000 - 0 dB, minimum gain setting  
0000001 - 0.5 dB gain  
0000010 - 1.0 dB gain  
...  
[6:0]  
gain[6:0]  
7
0000000  
1001110 - 39 dB gain  
1001111 - 39.5 dB gain  
1010000 - 40 dB, maximum gain setting  
Reg 02h[5] = 1 and Reg 02h[6] = 1  
(i.e. SPI gain control & gain decode bypassed)  
[23:7]  
unused  
[3][4]  
taꢇlꢆ 11. rꢆꢃ 03h - gaꢀꢂ Coꢂꢁꢄol rꢆꢃꢀsꢁꢆꢄ, WHen nOt usꢀꢂꢃ dꢆcodꢆ loꢃꢀc  
Bit  
Name  
Width  
Default  
Description  
gain[8:0] define the VGA I and Q channel gain when Reg 02h[5] = 1 and  
Reg 02h[6] = 1 (i.e. SPI gain control and gain decode bypassed)  
Generally the first 4 bits control the 1st and 3rd stage while the last 5  
bits control the 2nd stage gain.  
x001nnnnn - 1st stage set to 0 dB  
x010nnnnn - 1st stage set to 10 dB  
x100nnnnn - 1st stage set to 20 dB  
[8:0]  
gain[8:0]  
9
000000000  
0xxxnnnnn - 3rd stage set to 0 dB  
1xxxnnnnn - 3rd stage set to 10 dB  
xxxxnnnnn - 2nd stage set as follows:  
nnnnn = 00000 - set to 0 dB  
nnnnn = 00001 - set to 0.5 dB  
nnnnn = 10011 - set to 9.5 dB  
nnnnn = 10100 - set to 10 dB  
[23:9]  
unused  
[1] Reg 03h bit assignment depends on the setting of bits 5 and 6 in Reg 02h. If Reg 02h[5]=0, then all Reg 03h bits are ignored (parallel port selected)  
[2] For Reg 02h[5]=1 and Reg 02h[6]=0, gain control is via an SPI register with decode, and Reg 03h[6:0] are used as follows.  
[3] Note that the Parallel Port gain logic always uses the gain decode logic, and therefore the bit encoding is the same as Reg 03h - Gain Control  
Register WHEN USING decode logic.  
[4] For Reg 02h[5]=1 and Reg 02h[6]=1, gain control is via an SPI register without decode, and Reg 03h[6:0] are used as follows.  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
For price, delivery, and to place orders: Analog Devices, Inc.,  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
Phone: 781-329-4700 • Order online at www.analog.com  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
20  
Application Support: Phone: 1-800-ANALOG-D  
Trademarks and registered trademarks are the property of their respectiveowners.

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