Datasheet > HMAT14JWRLB189N

HMAT14JWRLB189N

更新时间： 2023-12-06 20:06:15

品牌	Logo	应用领域
海力士 - HYNIX		/
页数	文件大小	规格书
68页	2667K
描述
LRDIMM

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数据手册

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HMAT14JWRLB189N 数据手册

Pin Descriptions

Pin Name

Description

Pin Name

Description

A0-A17¹

BA0, BA1

BG0, BG1

I²C serial bus clock for SPD-TSE

I²C serial data line for SPD-TSE

I²C slave address select for SPD-TSE

SDRAM parity input

SDRAM address bus

SDRAM bank select

SCL

SDA

SDRAM bank group select

SA0-SA2

PAR

RAS_n²

CAS_n³

WE_n⁴

SDRAM row address strobe input

SDRAM column address strobe input

SDRAM write enable input

VDD

SDRAM core power supply

CS0_n, CS1_n,

CS2_n, CS3_n

DIMM Rank Select Lines input

SDRAM clock enable lines input

C0, C1, C2

VREFCA

VSS

Chip ID lines for 3DS SDRAMs

SDRAM command/address reference

supply

CKE0, CEK1

ODT0, ODT1

SDRAM on-die termination control lines

input

Power supply return (ground)

ACT_n

DQ0-DQ63

CB0-CB7

SDRAM activate

VDDSPD

ALERT_n

VPP

Serial SPD-TSE positive power supply

SDRAM alert_n

DIMM memory data bus

DIMM ECC check bits

SDRAM Supply

TDQS9_t-TDQS17_t

TDQS9_c-TDQS17_c

Dummy loads. Not used on LRDIMMs

SDRAM data strobes

Optional power Supply on socket but

not used on LRDIMM

DQS0_t-DQS17_t

DQS0_c-DQS17_c

12V

(positive line of differential pair)

SDRAM data strobes

RESET_n

EVENT_n

Set DRAMs to a Known State

(negative line of differential pair)

Data Bus Inversion. Not used on

LRDIMMs

SPD-TSE signals a thermal event has

occurred

DBI0_n-DBI8_n

DM0_n-DM8_n

CK0_t, CK1_t

Data Mask. Not used on LRDIMMs

SDRAM clocks input (positive line of dif-

ferential pair)

VTT

RFU

SDRAM I/O termination supply

Reserved for future use

SDRAM clocksinput (negative line of

differential pair)

CK0_c, CK1_c

1. Address A17 is only valid for 16Gbx4 based SDRAMs.

2. RAS_n is a multiplexed function with A16.

3. CAS_n is a multiplexed function with A15.

4. WE_n is a multiplexed function with A14.

Rev. 1.0 / Nov.2020

1 2 3 456 7 8...68

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