Pin Descriptions
Pin Name
Description
Pin Name
Description
I2C serial bus clock for SPD-TSE and
register
A0-A171
BA0, BA1
BG0, BG1
Register address input
SCL
I2C serial data line for SPD-TSE and
register
Regisiter bank select input
SDA
I2C slave address select for SPD-TSE
and register
Regisiter bank group select input
SA0-SA2
RAS_n2
CAS_n3
WE_n4
Register row address strobe input
Register column address strobe input
Register write enable input
PAR
VDD
Register parity input
SDRAM core power supply
Chip ID lines for SDRAMx
C0, C1, C2
CS0_n, CS1_n,
CS2_n, CS3_n
Optional Power Supply on socket but
not used on RDIMM
DIMM Rank Select Lines input
Register clock enable lines input
12V
VREFCA
VSS
SDRAM command/address reference
supply
CKE0, CEK1
ODT0, ODT1
Register on-die termination control
lines input
Power supply return (ground)
ACT_n
DQ0-DQ63
CB0-CB7
Register input for activate input
DIMM memory data bus
DIMM ECC check bits
VDDSPD
ALERT_n
VPP
Serial SPD/TS positive power supply
Register ALERT_n output
SDRAM Supply
TDQS9_t-TDQS17_t Dummy loads for mixed populations of
TDQS9_c-TDQS17_c x4 based and x8 based RDIMMs.
Data Buffer data strobes
DQS0_t-DQS17_t
DM0_n-DM8_n Data Mask
(positive line of differential pair)
Data Buffer data strobes
DQS0_c-DQS17_c
Set Register and SDRAMs to a Known
State
RESET_n
EVENT_n
VTT
(negative line of differential pair)
SPD signals a thermal event has
occurred
DBI0_n-DBI8_n Data Bus Inversion
Register clock input (positive line of dif-
CK0_t, CK1_t
ferential pair)
SDRAM I/O termination supply
Reserved for future use
Register clocks input (negative line of
differential pair)
CK0_c, CK1_c
RFU
1. Address A17 is only valid for 16Gbx4 based SDRAMs.
2. RAS_n is a multiplexed function with A16.
3. CAS_n is a multiplexed function with A15.
4. WE_n is a multiplexed function with A14.
Rev. 1.0 / Feb.2020
5