Symbol
Type
Function
Address Inputs: Provide the row address for ACTIVATE Commands and the column
address for Read/Write commands to select one location out of the memory array in the
A0 - A16
Input respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have
additional functions. See other rows. The address inputs also provide the op-code during
Mode Register Set commands.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write
operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a
Precharge command to determine whether the Precharge applies to one bank (A10
A10 / AP
Input
LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank addresses.
Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if
Input burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped).
See command truth table for details.
A12 / BC_n
RESET_n
CMOS Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive
Input when RESET_n is HIGH. RESET_n must be HIGH during normal operation.
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then
Input/ CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the
Output internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor
specific data sheets to determine which DQ is used.
DQ
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. DDR4 SDRAMs support differential data strobe only and does not
support single-ended.
Input/
Output
DQS_t, DQS_c,
Command and Address Parity Input : DDR4 Supports Even Parity check in DRAMs with
MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity with
Input ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A16-A0. Input parity
should be maintained at the rising edge of the clock and at the same time with
command & address with CS_n LOW.
PARITY
ALERT: It has multiple functions, such as CRC error flag, Command and Address Parity
error flag, as an Output signal. If there is an error in CRC, then ALERT_n goes LOW for
the period time interval and goes back HIGH. If there is an error in Command Address
Output Parity Check, then ALERT_n goes LOW for a relatively long period until on going DRAM
internal recovery transaction is complete.
ALERT_n
Using this signal or not is dependent on the system.
This is an open drain signal. It requires a pullup resistor on the system.
EVENT_n
SAVE_n
Output I2C thermal event indicator. Open drain, requires a pullup resistor on the system.
Input/ Not used on SODIMMs. SODIMMs will have no connection to this pin. See specifications
Output of NVDIMMs for signal description.
Bus clock used to strobe data into and out of I2C devices. Open drain and requires a
pullup resistor on the system.
SCL
Input
Input/
SDA
I2C data. Open drain and requires a pullup resistor on the system.
Output
Rev. 1.1 / Aug.2019
7
5秒后页面跳转
MAX6675资料手册参数详解、引脚配置说明
LM258引脚图及功能介绍、主要参数分析
CD4052资料手册参数详解、引脚配置说明
一文带你了解TPS5430资料手册分析：参数介绍、引脚配置说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
