Datasheet > HMAA4GS7AJR8N-WMT0

HMAA4GS7AJR8N-WMT0

更新时间： 2023-12-06 20:03:59

品牌	Logo	应用领域
海力士 - HYNIX		/
页数	文件大小	规格书
73页	1539K
描述
ECC-SODIMM

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数据手册

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HMAA4GS7AJR8N-WMT0 数据手册

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Pin Descriptions

Pin Name

Description

Pin Name

Description

SDRAM address bus

SDRAM bank select

SCL

SDA

A0-A16

BA0, BA1

BG0, BG1

I²C serial bus clock for SPD-TSE

I²C serial bus line for SPD-TSE

I²C slave address select for SPD-TSE

SDRAM parity input

SDRAM bank group select

SDRAM row address strobe

SDRAM column address strobe

SDRAM write enable

SA0-SA2

PARITY

VDD

RAS_n¹

CAS_n²

WE_n³

SDRAM I/OO and core power supply

SDRAM activating power supply

VPP

CS0_n, CS1_n,

CS2_n, CS3_n

Rank Select Lines

C0, C1

VREFCA

VSS

Chip ID lines for 3DS components

SDRAM command/address reference

supply

CKE0, CEK1

ODT0, ODT1

SDRAM clock enable lines input

SDRAM on-die termination control

lines input

Power supply return (ground)

ACT_n

DQ0-DQ63

CB0-CB7

SDRAM activate

VDDSPD

ALERT_n

Serial SPD-TSE positive power supply

SDRAM ALERT_n output

DIMM memory data bus

DIMM ECC check bits

SDRAM data strobes

DQS0_t-DQS8_t

DQS0_c-DQS8_c

RESET_n

EVENT_n

VTT

Set DRAMs to a Known State

(positive line of differential pair)

SDRAM data strobes

SPD signals a thermal event has

occurred

(negative line of differential pair)

SDRAM data masks/data bus inersion

(x8-based x72 DIMMs)

DM0_n-DM8_n,

DBI0_n-DBI8_n

SDRAM I/O termination supply

No connection

SDRAM clock (positive line of differen-

tial pair)

CK0_t, CK1_t

CK0_c, CK1_c

SDRAM clock (positive line of differen-

tial pair)

1. RAS_n is a multiplexed function with A16.

2. CAS_n is a multiplexed function with A15.

3. WE_n is a multiplexed function with A14.

Rev. 1.1 / Aug.2019

1 2 3 456 7 8...73

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