Symbol
Type
Function
Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write, or
Precharge command is being applied. BG0 also determines which mode register is to be
accessed during a MRS cycle. x4/x8 SDRAM configurations have BG0 and BG1. x16
based SDRAMs only have BG0.
BG0, BG1
Input
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or
BA0, BA1
A0 - A17
Input Precharge command is being applied. Bank address also determines which mode
register is to be accessed during a MRS cycle.
Address Inputs: Provide the row address for ACTIVATE Commands and the column
address for Read/Write commands to select one location out of the memory array in the
respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have
additional functions. See other rows. The address inputs also provide the op-code during
Input
Mode Register Set commands.
A17 is only defined for the x4 SDRAM configuration.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write
operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a
Precharge command to determine whether the Precharge applies to one bank (A10
A10 / AP
Input
LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank addresses.
Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if
Input burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped).
See command truth table for details.
A12 / BC_n
RESET_n
DQ
CMOS Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive
Input when RESET_n is HIGH. RESET_n must be HIGH during normal operation.
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then
CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the
internal Vref level during test via Mode Register Setting MR4 A4=High.
Input/
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7;
Input/ DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t and
Output DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively,
to provide differential pair signaling to the system during reads and writes. DDR4
SDRAM supports differential data strobe only and does not support single-ended.
DQS_t, DQS_c,
DQSU_t, DQSU_c,
DQSL_t, DQSL_c
TDQS_t, TDQS_c Output Termination Data Strobe: TDQS_t/TDQS_c are not valid for UDIMMs.
Command and Address Parity Input : DDR4 Supports Even Parity check in DRAMs with
MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity with
PARITY
Input ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A16-A0. Input parity
should be maintained at the rising edge of the clock and at the same time with
command & address with CS_n LOW.
Rev. 1.5 / Jul.2020
7
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