Datasheet > HMA82GU7MFR8N-PB

HMA82GU7MFR8N-PB

更新时间： 2024-01-18 18:41:07

品牌	Logo	应用领域
海力士 - HYNIX		时钟
页数	文件大小	规格书
61页	928K
描述
Memory IC, 2GX72, CMOS,

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中文翻译

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技术参数
数据手册

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HMA82GU7MFR8N-PB 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	, DIMM288,33	Reach Compliance Code：	compliant
风险等级：	5.84	最长访问时间：	0.225 ns
最大时钟频率 (fCLK)：	800 MHz	I/O 类型：	COMMON
内存密度：	154618822656 bit	内存宽度：	72
端子数量：	288	字数：	2147483648 words
字数代码：	2000000000	最高工作温度：	85 °C
最低工作温度：		组织：	2GX72
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装等效代码：	DIMM288,33	电源：	1.2 V
认证状态：	Not Qualified	刷新周期：	8192
子类别：	Other Memory ICs	标称供电电压 (Vsup)：	1.2 V
表面贴装：	NO	技术：	CMOS
温度等级：	OTHER	Base Number Matches：	1

HMA82GU7MFR8N-PB 数据手册

Input/Output Functional Descriptions

Symbol

Type

Function

CK0_t, CK0_c,

CK1_t, CK1_c

Clock: CK_t and CK_c are differential clock inputs. All address and control input signals

are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.

Input

Clock Enable: CKE HIGH activates and CKE Low deactivates internal clock signals and

device input buffers and output drivers. Taking CKE Low provides Precharge Power-

Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in

any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref

CKE0, CKE1

Input have become stable during the power on and initialization sequence, they must be

maintained during all operations (including Self-Refresh). CKE must be maintained high

throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE,

are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-

Refresh.

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for

CS0_n, CS1_n,

CS2_n, CS3_n

external Rank selection on systems with multiple Ranks. CS_n is considered part of the

command code.

Input

CS2_n and CS_3 are not used on UDIMMs.

Chip ID: Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of

Input stacked compnent. Chip ID is considered part of the command code.

Not used on UDIMMs.

C0, C1, C2

ODT0, ODT1

ACT_n

On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance

internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t,

DQS_c and DM_n/DBI_n/TDQS_t,NU/TDQS_c (When TDQS is enabled via Mode

Input

applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal.

The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.

Activation Command Input: ACT_n defines the Activation command being entered along

Input with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as

Row Address A16, A15 and A14.

Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the

command being entered. Those pins have multi function. For example, for activation

Input with ACT_n Low, these are Addresses like A16, A15 and A14 but for non-activation

command with ACT_n High, these are Command pins for Read, Write and other

command defined in command truth table.

RAS_n/A16,

CAS_n/A15,

WE_n/A14

Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.

Input data is masked when DM_n is sampled LOW coincident with that input data during

a Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function

by Mode Register A10, A11, A12 setting in MR5. For x8 device, the function of DM or

TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output

identifing wherther to store/output the true or inverted data. If DBI_n is LOW, the data

will be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is

HIGH. TDQS is only supported in x8.

DM_n/DBI_n/

TDQS_t,

(DMU_n/DBIU_n), Output

(DML_n/DBIL_n)

Input/

TDQS is not valid for UDIMMs.

Rev. 0.1 / Mar. 2015

1...3 4 567 8 9...61

中文翻译

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HMA82GU7MFR8N-TF	HYNIX	获取价格	DDR4 SDRAM Unbuffered DIMM Based on 8Gb M-die
HMA82GU7MFR8N-UH	HYNIX	获取价格	DDR4 SDRAM Unbuffered DIMM Based on 8Gb M-die
HMA82GU8CJR8N-UHT0	HYNIX	获取价格	ECC-UDIMM
HMA82GU8CJR8N-VKT0	HYNIX	获取价格	ECC-UDIMM
HMA84GR7CJR4N-UHT2	HYNIX	获取价格	RDIMM
HMA84GR7CJR4N-UHTD	HYNIX	获取价格	RDIMM
HMA84GR7CJR4N-UHTN	HYNIX	获取价格	RDIMM
HMA84GR7CJR4N-VKT3	HYNIX	获取价格	RDIMM
HMA84GR7CJR4N-VKTF	HYNIX	获取价格	RDIMM
HMA84GR7CJR4N-VKTN	HYNIX	获取价格	RDIMM

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