Datasheet > HI1-565ASD-2

HI1-565ASD-2

更新时间： 2024-02-25 09:03:25

品牌	Logo	应用领域
英特矽尔 - INTERSIL		转换器
页数	文件大小	规格书
9页	288K
描述
High Speed, Monolithic D/A Converter with Reference

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技术参数
数据手册

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HI1-565ASD-2 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP24,.6	Reach Compliance Code：	unknown
ECCN代码：	3A001.A.2.C	HTS代码：	8542.39.00.01
风险等级：	5.16	最大模拟输出电压：	10 V
最小模拟输出电压：	-10 V	转换器类型：	D/A CONVERTER
输入位码：	BINARY, OFFSET BINARY, 2'S COMPLEMENT BINARY	输入格式：	PARALLEL, WORD
JESD-30 代码：	R-CDIP-T24	JESD-609代码：	e0
最大线性误差 (EL)：	0.018%	标称负供电电压：	-15 V
位数：	12	功能数量：	1
端子数量：	24	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP	封装等效代码：	DIP24,.6
封装形状：	RECTANGULAR	封装形式：	IN-LINE
电源：	+-15 V	认证状态：	Not Qualified
最大稳定时间：	1 µs	标称安定时间 (tstl)：	0.35 µs
子类别：	Other Converters	最大压摆率：	14.5 mA
标称供电电压：	15 V	表面贴装：	NO
技术：	BIPOLAR	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
Base Number Matches：	1

HI1-565ASD-2 数据手册

HI-565A

100Ω

REF OUT

BIP.

OFF.

100Ω

20V SPAN

HI-565A

10V

10V SPAN

REF

9.95K

DAC

0.5mA

19.95K

REF

DAC

OUT

(4 x I

REF

x CODE)

2.5K

3.5K

REF

GND

(SEE

TABLE 2)

CODE

INPUT

24 13

MSB LSB

-V

PWR

GND

FIGURE 2. BIPOLAR VOLTAGE OUTPUT

(Cases (b) and (c) may be eliminated unless the overshoot

exceeds 0.5 LSB). For example, refer to Figure 3 for the

measurement of case (d).

Settling Time

This is a challenging measurement, in which the result

depends on the method chosen, the precision and quality of

test equipment and the operating conﬁguration of the DAC

(test conditions). As a result, the different techniques in use

by converter manufacturers can lead to consistently different

results. An engineer should understand the advantage and

limitations of a given test method before using the speciﬁed

settling time as a basis for design.

Procedure

As shown in Figure 3B, settling time equals t plus the

comparator delay (t = 15ns). To measure t :

• Adjust the delay on generator No. 2 for a t of several

microseconds. This assures that the DAC output has

settled to its ﬁnal value.

The previous approach calls for a strobed comparator to

sense final perturbations of the DAC output waveform. This

gives the LSB a reasonable magnitude (814µV for the

HI-565A), which provides the comparator with enough

overdrive to establish an accurate ±0.5 LSB window about the

final settled value. Also, the required test conditions simulate

the DACs environment for a common application - use in a

successive approximation A/D converter. Considerable

experience has shown this to be a reliable and repeatable way

to measure settling time.

• Switch on the LSB (+5V).

• Adjust the V

LSB

supply for 50% triggering at

COMPARATOR OUT. This is indicated by traces of

equal brightness on the oscilloscope display as shown

in Figure 3B. Note DVM reading.

• Switch the LSB to Pulse (P).

• Readjust the V

supply for 50% triggering as before,

LSB

and note DVM reading. One LSB equals one tenth the

difference in the DVM readings noted above.

The usual speciﬁcation is based on a 10V step, produced by

• Adjust the V

LSB

supply to reduce the DVM reading by 5

simultaneously switching all bits from off-to-on (t ) or on-

LSBs (DVM reads 10X, so this sets the comparator to

sense the ﬁnal settled value minus 0.5 LSB).

Comparator output disappears.

to-off (t

OFF

). The slower of the two cases is speciﬁed, as

measured from 50% of the digital input transition to the ﬁnal

entry within a window of ±0.5 LSB about the settled value.

Four measurements characterize a given type of DAC:

• Reduce generator No. 2 delay until comparator output

reappears, and adjust for “equal brightness”.

(a)

(b)

(c)

(d)

, to ﬁnal value +0.5 LSB

, to ﬁnal value -0.5 LSB

• Measure t from scope as shown in Figure 3B. Settling

time equals t + t , i.e., t + 15ns.

, to ﬁnal value +0.5 LSB

OFF

, to ﬁnal value -0.5 LSB

OFF

1...3 4 567 8 9

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