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HI1-565ASD-2 PDF预览

HI1-565ASD-2

更新时间: 2024-01-02 01:24:45
品牌 Logo 应用领域
英特矽尔 - INTERSIL 转换器
页数 文件大小 规格书
9页 288K
描述
High Speed, Monolithic D/A Converter with Reference

HI1-565ASD-2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP24,.6Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.16最大模拟输出电压:10 V
最小模拟输出电压:-10 V转换器类型:D/A CONVERTER
输入位码:BINARY, OFFSET BINARY, 2'S COMPLEMENT BINARY输入格式:PARALLEL, WORD
JESD-30 代码:R-CDIP-T24JESD-609代码:e0
最大线性误差 (EL):0.018%标称负供电电压:-15 V
位数:12功能数量:1
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP24,.6
封装形状:RECTANGULAR封装形式:IN-LINE
电源:+-15 V认证状态:Not Qualified
最大稳定时间:1 µs标称安定时间 (tstl):0.35 µs
子类别:Other Converters最大压摆率:14.5 mA
标称供电电压:15 V表面贴装:NO
技术:BIPOLAR温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

HI1-565ASD-2 数据手册

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HI-565A  
Power Supply Sensitivity is a measure of the change in  
Definitions of Specifications  
gain and offset of the D/A converter resulting from a change  
in -15V or +15V supplies. It is specified under DC conditions  
and expressed as parts per million of full scale range per  
percent of change in power supply (ppm of FSR/%).  
Digital Inputs  
The HI-565A accepts digital input codes in binary format and  
may be user connected for any one of three binary codes.  
Straight Binary, Two’s Complement (Note 5), or Offset  
Binary, (See Operating Instructions).  
Compliance Voltage is the maximum output voltage range  
that can be tolerated and still maintain its specified accuracy.  
Compliance Limit implies functional operation only, and  
makes no claims to accuracy.  
TABLE 1.  
ANALOG OUTPUT  
(NOTE 5)  
Glitch a glitch on the output of a D/A converter is a transient  
spike resulting from unequal internal ON-OFF switching  
times. Worst case glitches usually occur at half-scale or the  
major carry code transition from 011...1 to 100...0 or vice  
versa. For example, if turn ON is greater than turn OFF for  
011...1 to 100...0, an intermediate state of 000...0 exists,  
such that, the output momentarily glitches toward zero  
output. Matched switching times and fast switching will  
reduce glitches considerably.  
DIGITAL  
INPUT  
STRAIGHT  
BINARY  
OFFSET  
BINARY  
TWO'S  
COMPLEMENT  
MSB...LSB  
000...000  
Zero  
1
-FS  
(Full Scale)  
Zero  
100...000  
111...111  
011...111  
NOTE:  
/ FS  
2
Zero  
-FS  
+FS - 1 LSB  
+FS - 1 LSB  
Zero - 1 LSB  
Zero - 1 LSB  
+FS - 1 LSB  
1/2FS - 1 LSB  
Detailed Description  
Op Amp Selection  
5. Invert MSB with external inverter to obtain Two’s Complement  
Coding.  
The Hl-565As current output may be converted to voltage  
using the standard connections shown in Figures 1 and 2.  
The choice of operational amplifier should be reviewed for  
each application, since a significant trade-off may be made  
between speed and accuracy.  
Nonlinearity of a D/A converter is an important measure of  
its accuracy. It describes the deviation from an ideal straight  
line transfer curve drawn between zero (all bits OFF) and full  
scale (all bits ON) (End Point Method).  
For highest precision, use an HA-5130. This amplifier  
contributes negligible error, but requires about 11µs to settle  
within ±0.1% following a 10V step.  
Differential Nonlinearity for a D/A converter, it is the  
difference between the actual output voltage change and the  
ideal (1 LSB) voltage change for a one bit change in code. A  
Differential Nonlinearity of ±1 LSB or less guarantees  
monotonicity; i.e., the output always increases for an  
increasing input.  
The Intersil HA-2600 is the best all-around choice for this  
application, and it settles in 1.5µs (also to ±0.1% following a  
10V step). Remember, settling time for the DAC amplifier  
2
2
combination is the square root of t plus t , where t , t  
D
A
D A  
Settling Time is the time required for the output to settle to  
within the specified error band for any input code transition.  
It is usually specified for a full scale or major carry transition,  
settling to within ±0.5 LSB of final value.  
are settling times for the DAC and amplifier.  
No-Trim Operation  
The Hl-565A will perform as specified without calibration  
adjustments. To operate without calibration, substitute 50Ω  
resistors for the 100trimming potentiometers: In Figure 1  
replace R2 with 50also remove the network on pin 8 and  
connect 50to ground. For bipolar operation in Figure 2,  
replace R3 and R4 with 50resistors.  
Gain Drift is the change in full scale analog output over the  
specified temperature range, expressed in parts per million  
o
o
of full scale range per C (ppm of FSR/ C). Gain error is  
o
measured with respect to 25 C at high (T ) and low (T )  
H
L
temperatures. Gain drift is calculated for both high (T  
H
o
o
-25 C) and low ranges (25 C -T ) by dividing the gain error  
L
With these changes, performance is guaranteed as shown  
under Specifications, “External Adjustments”. Typical unipolar  
zero will be ±0.5 LSB plus the op amp offset.  
by the respective change in temperature. The specification is  
the larger of the two representing worst-case drift.  
Offset Drift is the change in analog output with all bits OFF  
The feedback capacitor, C, must be selected to minimize  
settling time.  
over the specified temperature range expressed in parts per  
o
o
million of full scale range per C (ppm of FSR/ C). Offset  
o
Calibration  
error is measured with respect to 25 C at high (T ) and low  
H
(T ) temperatures. Offset Drift is calculated for both high (T  
Calibration provides the maximum accuracy from a  
converter by adjusting its gain and offset errors to zero. For  
the Hl-565A, these adjustments are similar whether the  
current output is used, or whether an external op amp is  
L
H
o
o
-25 C) and low (25 C -T ) ranges by dividing the offset error  
L
by the respective change in temperature. The specification  
given is the larger of the two, representing worst-case drift.  
4

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