HI-8482
PIN DESCRIPTION TABLE
SYMBOL FUNCTION
DESCRIPTION
SYMBOL FUNCTION
DESCRIPTION
CAP1A
CAP1B
CAP2A
CAP2B
INPUT
INPUT
INPUT
INPUT
Filter capacitor input for terminal A of
channel 1
IN2B
OUT1A
OUT1B
OUT2A
OUT2B
TESTA
TESTB
+VL
INPUT
ARINC input terminal B of channel 2
OUTPUT TTL output terminal A of channel 1
OUTPUT TTL output terminal B of channel 1
OUTPUT TTL output terminal A of channel 2
OUTPUT TTL output terminal B of channel 2
Filter capacitor input for terminal B of
channel 1
Filter capacitor input for terminal A of
channel 2
Filter capacitor input for terminal B of
channel 2
INPUT
INPUT
Test input terminal A
Test input terminal B
GND
IN1A
IN1B
IN2A
POWER 0 Volts
INPUT
INPUT
INPUT
ARINC input terminal A of channel 1
POWER +5 Volts ±10%
ARINC input terminal B of channel 1
ARINC input terminal A of channel 2
+Vs
POWER +12 Volts ±10% or +15 Volts ±10%
POWER -12 Volts ±10% or -15 Volts ±10%
-Vs
TIMING DIAGRAMS
+10V
ARINC
DIFFERENTIAL
INPUT
0V
tPLH
-10V
tr
tf
90%
10%
50%
OUTA
OUTB
tPHL
tPHL
tPLH
50%
FIGURE 4.
+5V
0V
TESTA
TESTB
+5V
0V
tTLH
tr
tf
90%
10%
50%
OUTA (test)
OUTB (test)
tTHL
tTHL
tTLH
50%
FIGURE 5.
HOLT INTEGRATED CIRCUITS
4