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HFBR-5208XXXZ PDF预览

HFBR-5208XXXZ

更新时间： 2024-02-29 07:25:36
品牌 Logo 应用领域
安华高科 - AVAGO ATM异步传输模式
页数 文件大小 规格书
17页 237K
描述
1 x 9 Fiber Optic Transceivers for 622 Mb/s ATM/SONET/SDH Applications

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中文翻译

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HFBR-5208XXXZ 数据手册

 浏览型号HFBR-5208XXXZ的Datasheet PDF文件第1页浏览型号HFBR-5208XXXZ的Datasheet PDF文件第2页浏览型号HFBR-5208XXXZ的Datasheet PDF文件第3页浏览型号HFBR-5208XXXZ的Datasheet PDF文件第5页浏览型号HFBR-5208XXXZ的Datasheet PDF文件第6页浏览型号HFBR-5208XXXZ的Datasheet PDF文件第7页 
Maintain a solid, low inductance ground plane for returning  
signal currents to the power supply. Multilayer plane printed  
and high, self-resonating frequency are recommended. All  
power supply components need to be placed physically  
circuit board is best for distribution of V , returning ground  
next to the V pins of the receiver and transmitter. Use a  
CC  
CC  
currents, forming transmission lines and shielding. Also, it  
is important to suppress noise from influencing the fiber-  
optic transceiver per-formance, especially the receiver  
good, uniform ground plane with a minimum number of  
holes to provide a low-inductance ground current return  
path for the signal and power supply currents.  
circuit. Proper power supply filtering of V for this trans-  
ceiver is accomplished by using the recommended sepa-  
rate filter circuits shown in Figure 4. These filter circuits  
CC  
Although the front mounting posts make contact with the  
metallized housing, these posts should not be relied upon to  
provide adequate electrical connection to the plated housing.  
It is recommended to either connect these front posts to  
chassis ground or allow them to remain unconnected. These  
front posts should not be connected to signal ground.  
suppress V noise of 100 mV peak-to-peak or less over  
CC  
a broad frequency range. This prevents receiver sensitiv-  
ity degradation . It is recommended that surface-mount  
components be used. Use tantalum capacitors for the 10  
μF capacitors and monolithic, ceramic bypass capacitors  
for the 0.1 μF capacitors. Also, it is recommended that a  
surface-mount coil inductor of 1 μH be used. Ferrite beads  
can be used to replace the coil inductors when using  
Figure 5 shows the recommended board layout pattern.  
In addition to these recommendations, AvagoTechnologies  
Application Engineering staff is available for consulting  
on best layout practices with various vendors’ serializer/  
deserializer, clock recovery/generation integrated circuits.  
quieter V supplies, but a coil inductor is recommended  
CC  
over a ferrite bead to provide low-frequency noise filtering  
as well. Coils with a low, series dc resistance (<0.7 ohms)  
NOTES:  
MOUNTING POST  
MOUNTING POST  
NO INTERNAL CONNECTION  
THE SPLIT-LOAD TERMINATIONS FOR PECL SIGNALS  
NEED TO BE LOCATED AT THE INPUT OF DEVICES  
RECEIVING THOSE PECL SIGNALS. RECOMMEND  
MULTI-LAYER PRINTED CIRCUIT BOARD WITH 50 OHM  
MICROSTRIP OR STRIPLINE SIGNAL PATHS BE USED.  
R1 = R4 = R6 = R8 = R10 = 130 OHMS.  
R2 = R3 = R5 = R7 = R9 = 82 OHMS.  
C1 = C2 = C3 = C5 = C6 = 0.1 F.  
NO INTERNAL CONNECTION  
HFBR-5208xxxZ  
TOP VIEW  
C4 = C7 = 10 F.  
L1 = L2 = 1 H COIL OR FERRITE INDUCTOR  
(see text comments).  
Rx  
V EER  
1
Rx  
V CCR  
5
Tx  
VCCT  
6
Tx  
V EET  
9
RD  
2
RD  
3
SD  
4
TD  
7
TD  
8
C1  
C2  
VCC  
R2  
R3  
C5  
L1  
L2  
C4  
C7  
TERMINATION  
AT PHY  
R1  
R4  
DEVICE  
VCC  
C3  
INPUTS  
V CC FILTER  
R5  
R7  
AT V PINS  
CC  
TRANSCEIVER  
R9  
TERMINATION  
AT TRANSCEIVER  
INPUTS  
C6  
R6  
R8  
R10  
RD  
RD  
SD  
VCC  
TD  
TD  
Figure 4. Recommended Circuit Schematic for dc Coupling (at +5 V) between Optical Transceiver and Physical Layer IC  
4
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