Datasheet > HEF4046BTD-T

HEF4046BTD-T

更新时间： 2024-02-05 06:43:50

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管
页数	文件大小	规格书
15页	408K
描述
IC PHASE LOCKED LOOP, PDSO16, PLL or Frequency Synthesis Circuit

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HEF4046BTD-T 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	SOP, SOP16,.25	Reach Compliance Code：	unknown
风险等级：	5.7	JESD-30 代码：	R-PDSO-G16
湿度敏感等级：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	5/15 V
认证状态：	Not Qualified	子类别：	PLL or Frequency Synthesis Circuits
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

HEF4046BTD-T 数据手册

Philips Semiconductors

Product speciﬁcation

HEF4046B

MSI

Phase-locked loop

PINNING

1. Phase comparator pulse output

2. Phase comparator 1 output

3. Comparator input

4. VCO output

5. Inhibit input

6. Capacitor C1 connection A

7. Capacitor C1 connection B

8. V_SS

9. VCO input

10. Source-follower output

11. Resistor R1 connection

12. Resistor R2 connection

13. Phase comparator 2 output

14. Signal input

15. Zener diode input for regulated supply.

Fig.2 Pinning diagram.

factor to obtain the maximum lock range. The average

output voltage of the phase comparator is equal to ¹⁄₂V_DD

when there is no signal or noise at the signal input. The

average voltage to the VCO input is supplied by the

low-pass filter connected to the output of phase

comparator 1. This also causes the VCO to oscillate at the

centre frequency (f_o). The frequency capture range (2 f_c) is

defined as the frequency range of input signals on which

the PLL will lock if it was initially out of lock. The frequency

lock range (2 f_L) is defined as the frequency range of input

signals on which the loop will stay locked if it was initially

in lock. The capture range is smaller or equal to the lock

range.

FUNCTIONAL DESCRIPTION

VCO part

The VCO requires one external capacitor (C1) and one or

two external resistors (R1 or R1 and R2). Resistor R1 and

capacitor C1 determine the frequency range of the VCO.

Resistor R2 enables the VCO to have a frequency off-set

if required. The high input impedance of the VCO simplifies

the design of low-pass filters; it permits the designer a wide

choice of resistor/capacitor ranges. In order not to load the

low-pass filter, a source-follower output of the VCO input

voltage is provided at pin 10. If this pin (SF_OUT) is used, a

load resistor (R_SF) should be connected from this pin to

V_SS; if unused, this pin should be left open. The VCO

output (pin 4) can either be connected directly to the

comparator input (pin 3) or via a frequency divider. A LOW

level at the inhibit input (pin 5) enables the VCO and the

source follower, while a HIGH level turns off both to

minimize stand-by power consumption.

With phase comparator 1, the range of frequencies over

which the PLL can acquire lock (capture range) depends

on the low-pass filter characteristics and this range can be

made as large as the lock range. Phase comparator 1

enables the PLL system to remain in lock in spite of high

amounts of noise in the input signal. A typical behaviour of

this type of phase comparator is that it may lock onto input

frequencies that are close to harmonics of the VCO centre

frequency. Another typical behaviour is, that the phase

angle between the signal and comparator input varies

between 0° and 180° and is 90° at the centre frequency.

Figure 3 shows the typical phase-to-output response

characteristic.

Phase comparators

The phase-comparator signal input (pin 14) can be

direct-coupled, provided the signal swing is between the

standard HE4000B family input logic levels. The signal

must be capacitively coupled to the self-biasing amplifier

at the signal input in case of smaller swings. Phase

comparator 1 is an EXCLUSIVE-OR network. The signal

and comparator input frequencies must have a 50% duty

January 1995

1 234 5 6 7...15

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