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HD74AC194FP PDF预览

HD74AC194FP

更新时间: 2024-02-18 12:05:22
品牌 Logo 应用领域
瑞萨 - RENESAS 移位寄存器
页数 文件大小 规格书
8页 214K
描述
AC SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, EIAJ, FP-16DA

HD74AC194FP 技术参数

生命周期:Transferred零件包装代码:SOIC
包装说明:TSSOP,针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.35其他特性:ALSO OPRATES AT 5V VCC NOMINAL; HOLD MODE
计数方向:BIDIRECTIONAL系列:AC
JESD-30 代码:R-PDSO-G16长度:5 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT位数:4
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):15 ns
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:85 MHz
Base Number Matches:1

HD74AC194FP 数据手册

 浏览型号HD74AC194FP的Datasheet PDF文件第2页浏览型号HD74AC194FP的Datasheet PDF文件第3页浏览型号HD74AC194FP的Datasheet PDF文件第4页浏览型号HD74AC194FP的Datasheet PDF文件第5页浏览型号HD74AC194FP的Datasheet PDF文件第6页浏览型号HD74AC194FP的Datasheet PDF文件第7页 
HD74AC194  
4-bit Bidirectional Unviersal Shift Register  
REJ03D0259–0200Z  
(Previous ADE-205-379 (Z))  
Rev.2.00  
Jul.16.2004  
Description  
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a  
shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control  
inputs, and a direct overriding clear line. The register has four destinct modes of operation: parallel (broadside) load,  
shift right (in the direction Q0 toward Q3); shift left; inhibit clock (do nothing).  
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0  
and S1, high. The data are loaded into their respective flip-flops and appear at the out after the positive transition of  
the clock input. During loading, serial data flow is inhibited. Shift right is accosynchronously with the rising  
edge of the clock pulse when S0 is high and S1 is low. Serial date for this mothe shift right data input.  
When S0 is low and S1 is high, data shifts left synchronously and new data s left serial input.  
Clocking of the flip-flops is inhibited when both mode control inputs anputs should be  
changed only when the clock input is high.  
Features  
Asynchronous Master Reset  
Hole (Do Nothing) Mode  
Outputs Source/Sink 24 mA  
Ordering Information  
Part Name  
Package Typ
e Abbreviation Taping Abbreviation (Quantity)  
HD74AC194FPEL SOP-16 pin (J
HD74AC194RPEL SOP-16 pi
P  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
Notes: 1. Please consult thkage availability.  
2. The packages ished from the conventional products by adding V at the end of  
the packag
Rev.2.00, Jul.16.2004, page 1 of 7  

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