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HD74AC194FP PDF预览

HD74AC194FP

更新时间: 2024-01-29 00:29:13
品牌 Logo 应用领域
日立 - HITACHI 移位寄存器
页数 文件大小 规格书
11页 71K
描述
Parallel In Parallel Out, AC Series, 4-Bit, Bidirectional, True Output, CMOS, PDSO16, FP-16DA

HD74AC194FP 技术参数

生命周期:Transferred零件包装代码:SOIC
包装说明:TSSOP,针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.35其他特性:ALSO OPRATES AT 5V VCC NOMINAL; HOLD MODE
计数方向:BIDIRECTIONAL系列:AC
JESD-30 代码:R-PDSO-G16长度:5 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT位数:4
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):15 ns
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:85 MHz
Base Number Matches:1

HD74AC194FP 数据手册

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HD74AC194  
4-bit Bidirectional Unviersal Shift Register  
Description  
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may  
want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs,  
operating mode control inputs, and a direct overriding clear line. The register has four destinct modes of  
operation: parallel (broadside) load, shift right (in the direction Q0 toward Q3); shift left; inhibit clock (do  
nothing).  
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode  
control inputs, S0 and S1, high. The data are loaded into their respective flip-flops and appear at the output  
after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is  
accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial  
date for this mode is entered at the shift right data input. When S0 is low and S1 is high, data shifts left  
synchronously and new data is entered at the shifts left serial input. Clocking of the flip-flops is inhibited  
when both mode control inputs are low. The mode control inputs should be changed only when the clock  
input is high.  
Features  
Asynchronous Master Reset  
Hole (Do Nothing) Mode  
Outputs Source/Sink 24 mA  

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