Datasheet > HC125

HC125

更新时间： 2024-02-10 00:48:28

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
8页	64K
描述
QUAD BUS BUFFERS 3-STATE

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数据手册

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HC125 数据手册

74VHC125

QUAD BUS BUFFERS (3-STATE)

PRELIMINARY DATA

■

HIGH SPEED:t_PD=3.8ns (TYP.) atV_CC= 5V

LOW POWER DISSIPATION:

_CC=4 µA (MAX.) at T_A=25 ^oC

■

HIGH NOISEIMMUNITY:

V_NIH= V_NIL=28% V_CC(MIN.)

POWERDOWN PROTECTIONON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

|I_OH| = I_OL= 8 mA (MIN)

BALANCEDPROPAGATIONDELAYS:

t_PLHt_PHL

(Micro Package)

(TSSOPPackage)

■

ORDER CODES :

74VHC125M

74VHC125T

■

This device requires the 3-STATE control input G

to be set high to place the output into the high

impedance state.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface5V to 3V.

OPERATING VOLTAGERANGE:

V_CC(OPR)= 2V to 5.5V

PIN AND FUNCTION COMPATIBLEWITH

74 SERIES125

IMPROVED LATCH-UP IMMUNITY

LOWNOISE:V_OLP= 0.8V(Max.)

■

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2kV ESD immunity and transient excess

voltage.

DESCRIPTION

The 74VHC125 is an advanced high-speed

CMOS QUAD BUS BUFFERS fabricated with

sub-micron silicon gate and double-layer metal

wiring C²MOS technology.

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/8

June 1999

12 3 4 5 6 7 8

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