Datasheet > H5ANAG6NCJR-VKC

H5ANAG6NCJR-VKC

更新时间： 2023-12-06 20:01:44

品牌	Logo	应用领域
海力士 - HYNIX		双倍数据速率
页数	文件大小	规格书
47页	1895K
描述
DDR4

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数据手册

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H5ANAG6NCJR-VKC 数据手册

Description

The H5ANAG4NCJR-xxC, H5ANAG8NCJR-xxC, H5ANAG6NCJR-xxC are a 16Gb CMOS Double Data Rate IV

(DDR4) Synchronous DRAM, ideally suited for the main memory applications which requires large memory

density and high bandwidth. SK hynix 16Gb DDR4 SDRAMs offer fully synchronous operations referenced

to both rising and falling edges of the clock. While all addresses and control inputs are latched on the ris-

ing edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled

on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to

achieve very high bandwidth.

Device Features and Ordering Information

FEATURES

• VDD=VDDQ=1.2V +/- 0.06V

RTT_NOM switchable by ODT pin

• Asynchronous RESET pin supported

• ZQ calibration supported

• Fully differential clock inputs (CK, CK) operation

• Differential Data Strobe (DQS, DQS)

• On chip DLL align DQ, DQS and DQS transition with CK • TDQS (Termination Data Strobe) supported (x8 only)

transition

• Write Levelization supported

• DM masks write data-in at the both rising and falling

• 8 bit pre-fetch

edges of the data strobe

• This product in compliance with the RoHS directive.

• All addresses and control inputs except data, data

strobes and data masks latched on the rising edges of

• Internal Vref DQ level generation is available

the clock

• Write CRC is supported at all speed grades

• Maximum Power Saving Mode is supported

• Programmable CAS latency 9, 10, 11, 12, 13, 14, 15,

16, 17, 18, 19 and 20 supported

• TCAR(Temperature Controlled Auto Refresh) mode is

supported

• Programmable additive latency 0, CL-1, and CL-2

supported (x4/x8 only)

• LP ASR(Low Power Auto Self Refresh) mode is sup-

• Programmable CAS Write latency (CWL) = 9, 10, 11,

12, 14, 16, 18

ported

• Fine Granularity Refresh is supported

• Programmable burst length 4/8 with both nibble

sequential and interleave mode

• Per DRAM Addressability is supported

• Geardown Mode(1/2 rate, 1/4 rate) is supported

• Programable Preamble for read and write is supported

• Self Refresh Abort is supported

• BL switch on the fly

• 16banks

• AverageRefreshCycle (Tcaseof0 ^oC~95^oC)

- 7.8 µs at 0^oC ~ 85 ^oC

- 3.9 µs at 85^oC ~ 95 ^oC

• CA parity (Command/Address Parity) mode is sup-

ported

• Bank Grouping is applied, and CAS to CAS latency

(tCCD_L, tCCD_S) for the banks in the same or different

bank group accesses are available

• JEDEC standard 78ball FBGA(x4/x8) Driver strength

selected by MRS

• Dynamic On Die Termination supported

• DBI(Data Bus Inversion) is supported(x8)

• Two Termination States such as RTT_PARK and

Rev. 1.5 / Sep.2020

1 234 5 6 7...47

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