Datasheet > H5AN8G6NDJR-VKC

H5AN8G6NDJR-VKC

更新时间： 2023-12-06 20:01:43

品牌	Logo	应用领域
海力士 - HYNIX		双倍数据速率
页数	文件大小	规格书
46页	845K
描述
DDR4

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数据手册

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H5AN8G6NDJR-VKC 数据手册

Description

The H5AN8G4NDJR-*xxC, H5AN8G8NDJR-*xxC, H5AN8G6NDJR-*xxC is a 8Gb CMOS Double Data Rate IV

(DDR4) Synchronous DRAM, ideally suited for the main memory applications which requires large memory

density and high bandwidth. SK hynix 8Gb DDR4 SDRAMs offer fully synchronous operations referenced to

both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising

edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on

both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve

very high bandwidth.

Device Features and Ordering Information

FEATURES

• VDD=VDDQ=1.2V +/- 0.06V

• ZQ calibration supported

• Fully differential clock inputs (CK, CK) operation

• Differential Data Strobe (DQS, DQS)

• TDQS (Termination Data Strobe) supported (x8 only)

• Write Levelization supported

• On chip DLL align DQ, DQS and DQS transition with CK  • 8 bit pre-fetch

transition

• This product in compliance with the RoHS directive.

• DM masks write data-in at the both rising and falling 

• Internal Vref DQ level generation is available

• Write CRC is supported at all speed grades

• Maximum Power Saving Mode is supported

edges of the data strobe

• All addresses and control inputs except data, data

strobes and data masks latched on the rising edges of

the clock

• TCAR(Temperature Controlled Auto Refresh) mode is

supported

• Programmable CAS latency 9, 10, 11, 12, 13, 14, 15,

16, 17, 18, 19 and 20 supported

• LP ASR(Low Power Auto Self Refresh) mode is sup-

ported

• Programmable additive latency 0, CL-1, and CL-2 

• Fine Granularity Refresh is supported

supported (x4/x8 only)

• Per DRAM Addressability is supported

• Programmable CAS Write latency (CWL) = 9, 10, 11,

12, 14, 16, 18

• Geardown Mode(1/2 rate, 1/4 rate) is supported

• Programable Preamble for read and write is supported

• Self Refresh Abort is supported

• Programmable burst length 4/8 with both nibble

sequential and interleave mode



• BL switch on the fly

• 16banks

• CA parity (Command/Address Parity) mode is sup-

ported

• AverageRefreshCycle (Tcaseof0 ^oC~95^oC)

- 7.8 µs at 0^oC ~ 85 ^oC

• Bank Grouping is applied, and CAS to CAS latency

(tCCD_L, tCCD_S) for the banks in the same or different

bank group accesses are available

- 3.9 µs at 85^oC ~ 95 ^oC

• DBI(Data Bus Inversion) is supported(x8)

• JEDEC standard 78ball FBGA(x4/x8), 78ball FBGA(x16)

• Driver strength selected by MRS

• Dynamic On Die Termination supported

• Two Termination States such as RTT_PARK and

RTT_NOM switchable by ODT pin

• Asynchronous RESET pin supported

Rev. 1.4 / Apr.2020

1 234 5 6 7...46

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