GS8673ET18/36BK-675/625/550/500
4M x 18 (Top View)
1
2
3
VDD
VSS
NUI
VSS
NUI
VSS
NUI
NUI
VSS
VREF
QVLD1
VSS
NUI
NUI
VSS
NUI
VSS
NUI
VSS
VDD
4
5
6
7
8
9
10
VDDQ
NUI
11
VDD
VSS
NUI
12
13
VDD
VSS
MCH
(CFG)
VDD
VDDQ
NUIO
VDDQ
NUIO
VDDQ
NUIO
NUIO
VDDQ
NUIO
VDDQ
VSS
VDDQ
NUI
VDDQ
DQ0
VDDQ
DQ1
VDDQ
DQ2
DQ3
VDDQ
DQ4
VDDQ
VSS
MCL
MVQ
VSS
SA
MCL
ZQ
PZT1
PZT0
VSS
A
B
C
D
E
F
NC
(RSVD)
MCL
(SIOM)
VSS
MCL
SA
VDDQ
NUI
VDD
VDDQ
NUI
NUIO
VSS
DQ17
VSS
SA
VDDQ
SA
NC
(288 Mb)
NC
(144 Mb)
VDDQ
SA
VSS
NUI
V
VDD
NUI
VSS
SA
VSS
SA
VDD
NUI
NUIO
VSS
DQ16
VSS
SS
VDD
SA
VDDQ
MZT1
R/W
VSS
VDD
SA
VSS
NUI
NUI
VSS
SA
VSS
SA
NUI
NUIO
NUIO
VSS
DQ15
DQ14
VSS
G
H
J
VDDQ
NUI
VDDQ
SA
VDDQ
SA
VDDQ
NUI
NUI
VSS
KD1
KD1
VSS
DLL
VSS
MCH
VSS
NUI
VSS
TCK
TDO
VSS
KD0
KD0
VSS
MCH
VSS
RST
VSS
NUI
VSS
TMS
TDI
VSS
VREF
QVLD0
VSS
NUI
VDD
VSS
VDD
VDDQ
SA
VDD
VDDQ
SA
VDD
VSS
CQ1
CQ1
VSS
CK
CQ0
CQ0
VSS
K
L
CK
NUI
VSS
NUI
NUIO
VDDQ
NUIO
NUIO
VDDQ
NUIO
VDDQ
NUIO
VDDQ
DQ13
VDDQ
DQ12
DQ11
VDDQ
DQ10
VDDQ
DQ9
M
N
P
R
T
NUIO
NUIO
VSS
VDDQ
NUI
VDDQ
SA
VDDQ
SA
VDDQ
NUI
LD
DQ5
DQ6
VSS
NUI
MZT0
VDDQ
VSS
NUI
VDD
SA
VDD
SA
NUI
VSS
NUI
NUIO
VSS
VDD
NUI
VDD
NUI
DQ7
VSS
VDDQ
VDDQ
VSS
NUI
AZT1
VDD
U
V
W
Y
SA
(x18)
SA
(B2)
NUIO
VSS
VDDQ
NUI
VDDQ
NUI
DQ8
VSS
NC
(RSVD)
VSS
VDD
RLM0
ZT
MCL
MCL
VDD
VDDQ
VDDQ
VDDQ
VDD
RLM1
Notes:
1. Pins 5A, 7A, and 6B are reserved for future use. They must be tied Low.
2. Pins 9N and 5R are reserved for future use. They must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration.
5. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
7. Pin 9D is reserved as address pin SA for 144Mb devices. It is a true no-connect in this device.
8. Pin 7D is reserved as address pin SA for 288Mb devices. It is a true no-connect in this device.
9. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.
10. Pins 8W and 8Y are reserved for internal use only. They must be tied Low.
11. Pins 7B and 7W are reserved for future use. They are true no-connects in this device.
Rev: 1.06 12/2017
2/37
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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