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GS8672D19AGE-400T PDF预览

GS8672D19AGE-400T

更新时间: 2023-02-26 15:12:53
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
30页 839K
描述
Standard SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8672D19AGE-400T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LBGA,针数:165
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:0.45 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PBGA-B165JESD-609代码:e1
长度:17 mm内存密度:75497472 bit
内存集成电路类型:STANDARD SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:165字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX18封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.5 mm最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:15 mm

GS8672D19AGE-400T 数据手册

 浏览型号GS8672D19AGE-400T的Datasheet PDF文件第2页浏览型号GS8672D19AGE-400T的Datasheet PDF文件第3页浏览型号GS8672D19AGE-400T的Datasheet PDF文件第4页浏览型号GS8672D19AGE-400T的Datasheet PDF文件第5页浏览型号GS8672D19AGE-400T的Datasheet PDF文件第6页浏览型号GS8672D19AGE-400T的Datasheet PDF文件第7页 
Preliminary  
GS8672D19/37AE-400/375/333/300  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
400 MHz–300 MHz  
1.8 V V  
TM  
72Mb SigmaQuad-II+  
DD  
TM  
Burst of 4 ECCRAM  
1.5 V I/O  
Features  
Clocking and Addressing Schemes  
• 2.0 Clock Latency  
The GS8672D19/37AE SigmaQuad-II+ ECCRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are independent single-ended clock  
inputs, not differential inputs to a single differential clock input  
buffer.  
• On-Chip ECC with virtually zero SER  
• Simultaneous Read and Write SigmaQuad™ Interface  
• JEDEC-standard pinout and package  
• Dual Double Data Rate interface  
• Byte Write Capability  
• Burst of 4 Read and Write  
• On-Die Termination (ODT) on Data (D), Byte Write (BW),  
and Clock (K, K) outputs  
Because Separate I/O SigmaQuad-II+ B4 RAMs always  
transfer data in four packets, A0 and A1 are internally set to 0  
for the first read or write transfer, and automatically  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V HSTL Interface  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• Pin-compatible with present 9Mb, 18Mb, and 36Mb and  
future 144Mb devices  
incremented by 1 for the next transfers. Because the LSBs are  
tied off internally, the address field of a SigmaQuad-II+ B4  
RAM is always two address pins less than the advertised index  
depth (e.g., the 4M x 18 has a 1M addressable index).  
On-Chip Error Correction Code  
GSI's ECCRAMs implement an ECC algorithm that detects  
and corrects all single-bit memory errors, including those  
induced by Soft Error Rate (SER) events such as cosmic rays,  
alpha particles. The resulting SER of these devices is  
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude  
improvement over comparable ECCRAMs with no On-Chip  
ECC, which typically have an SER of 200 FITs/Mb or more.  
SER quoted above is based on reading taken at sea level.  
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
SigmaQuadECCRAM Overview  
The GS8672D19/37AE are built in compliance with the  
SigmaQuad-II+ ECCRAM pinout standard for Separate I/O  
synchronous ECCRAMs. They are 75,497,472-bit (72Mb)  
ECCRAMs. The GS8672D19/37AE SigmaQuad ECCRAMs  
are just one element in a family of low power, low voltage  
HSTL I/O ECCRAMs designed to operate at the speeds needed  
to implement economical high performance networking  
systems.  
However, the On-Chip Error Correction (ECC) will be  
disabled if a “Half Write” operation is initiated. See the Byte  
Write Contol section for further information.  
Parameter Synopsis  
-400  
2.5 ns  
0.45 ns  
-375  
-333  
3.0 ns  
0.45 ns  
-300  
3.3 ns  
0.45 ns  
tKHKH  
tKHQV  
2.66 ns  
0.45 ns  
Rev: 1.00 5/2010  
1/30  
© 2010, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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