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GS8662S08BGD-167IT PDF预览

GS8662S08BGD-167IT

更新时间: 2024-01-25 14:38:14
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
37页 763K
描述
Standard SRAM, 8MX8, 0.5ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216CAB-1, FPBGA-165

GS8662S08BGD-167IT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:BGA
包装说明:15 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216CAB-1, FPBGA-165针数:165
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.71
Is Samacsys:N最长访问时间:0.5 ns
其他特性:PIPELINED ARCHITECTUREJESD-30 代码:R-PBGA-B165
JESD-609代码:e1长度:15 mm
内存密度:67108864 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:165
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8MX8
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.4 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:13 mm
Base Number Matches:1

GS8662S08BGD-167IT 数据手册

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Preliminary  
GS8662S08/09/18/36BD-400/350/333/300/250  
72Mb SigmaSIOTM DDR -II  
Burst of 2 SRAM  
400 MHz–250 MHz  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
Features  
• Simultaneous Read and Write SigmaSIO™ Interface  
• JEDEC-standard pinout and package  
• Dual Double Data Rate interface  
• Byte Write controls sampled at data-in time  
• DLL circuitry for wide output data valid window and future  
frequency scaling  
• Burst of 2 Read and Write  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ mode pin for programmable output drive strength  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
Bottom View  
165-Bump, 13 mm x 15 mm BGA  
1 mm Bump Pitch, 11 x 15 Bump Array  
JEDEC Std. MO-216, Variation CAB-1  
SigmaSIOFamily Overview  
register clock inputs, C and C. If the C clocks are tied high, the  
K clocks are routed internally to fire the output registers  
instead. Each Burst of 2 SigmaSIO DDR-II SRAM also  
supplies Echo Clock outputs, CQ and CQ, which are  
synchronized with read data output. When used in a source  
synchronous clocking scheme, the Echo Clock outputs can be  
used to fire input registers at the data’s destination.  
GS8662S08/09/18/36BD are built in compliance with the  
SigmaSIO DDR-II SRAM pinout standard for Separate I/O  
synchronous SRAMs. They are 75,497,472-bit (72Mb)  
SRAMs. These are the first in a family of wide, very low  
voltage HSTL I/O SRAMs designed to operate at the speeds  
needed to implement economical high performance  
networking systems.  
Because Separate I/O Burst of 2 RAMs always transfer data in  
two packets, A0 is internally set to 0 for the first read or write  
transfer, and automatically incremented by 1 for the next  
transfer. Because the LSB is tied off internally, the address  
field of a Burst of 2 RAM is always one address pin less than  
the advertised index depth (e.g., the 4M x 18 has a 2M  
addressable index).  
Clocking and Addressing Schemes  
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous  
device. It employs dual input register clock inputs, K and K.  
The device also allows the user to manipulate the output  
register clock input quasi independently with dual output  
Parameter Synopsis  
-400  
2.5 ns  
0.45 ns  
-350  
2.86 ns  
0.45 ns  
-333  
3.0 ns  
0.45 ns  
-300  
3.3 ns  
0.45 ns  
-250  
4.0 ns  
0.45 ns  
tKHKH  
tKHQV  
Rev: 1.01 11/2010  
1/37  
© 2010, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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Standard SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216
GS8662S08BGD-300T GSI

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Standard SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216
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