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GS8322Z36AB-333IV PDF预览

GS8322Z36AB-333IV

更新时间： 2024-10-01 13:48:03
品牌 Logo 应用领域
GSI /
页数 文件大小 规格书
35页 507K
描述
119 BGA

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GS8322Z36AB-333IV 技术参数

是否Rohs认证： 不符合生命周期：Active
零件包装代码：BGA包装说明：BGA, BGA119,7X17,50
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
Factory Lead Time：8 weeks风险等级：5.47
最长访问时间：5 ns其他特性：ALSO OPERATED WITH 2.5V SUPPLY; PIPELINE/FLOW THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：333 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119长度：22 mm
内存密度：37748736 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：119字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
电源：1.8/2.5 V认证状态：Not Qualified
座面最大高度：1.99 mm最大待机电流：0.04 A
最小待机电流：1.7 V子类别：SRAMs
最大压摆率：0.295 mA最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
宽度：14 mm

GS8322Z36AB-333IV 数据手册

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GS8322Z18/36A(B/D)-xxxV  
333 MHz–150 MHz  
119 & 165 BGA  
Commercial Temp  
Industrial Temp  
36Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
Features  
Because it is a synchronous device, address, data inputs, and  
read/write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
• NBT (No Bus Turn Around) functionality allows zero wait  
Read-Write-Read bus utilization; fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 1.8 V or 2.5 V core power supply  
• 1.8 V or 2.5 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• ZQ mode pin for user-selectable high/low output drive  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 119- and 165-Bump BGA package  
• RoHS-compliant packages available  
The GS8322Z18/36A-xxxV may be configured by the user to  
operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, in addition to the rising-edge-  
triggered registers that capture input signals, the device  
incorporates a rising edge triggered output register. For read  
cycles, pipelined SRAM output data is temporarily stored by  
the edge-triggered output register during the access cycle and  
then released to the output drivers at the next rising edge of  
clock.  
Functional Description  
The GS8322Z18/36A-xxxV is a 36Mbit Synchronous Static  
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or  
other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS8322Z18/36A-xxxV is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
standard 119-bump or 165-bump BGA package.  
Parameter Synopsis  
-333  
-250  
-200  
-150  
Unit  
t
3.0  
3.0  
3.0  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x36)  
365  
425  
290  
345  
250  
290  
215  
240  
mA  
mA  
t
5.0  
5.0  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x36)  
270  
315  
245  
280  
210  
250  
200  
230  
mA  
mA  
Rev: 1.03 8/2013  
1/35  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...35

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