GS8161ExxD(GT/D)-xxxV
333 MHz–150 MHz
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Linear Burst Order (LBO) input. The Burst function need not be
used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Features
• FT pin for user-configurable flow through or pipeline operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode pin (Pin 14). Holding the FT mode pin low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered Data
Output Register.
• Automatic power-down for portable applications
• JEDEC-standard 165-bump BGA package
• RoHS-compliant 100-pin TQFP and 165 BGA packages available
DCD Pipelined Reads
The GS8161ExxD(GT/D)-xxxV is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Functional Description
Applications
The GS8161ExxD(GT/D)-xxxV is an 18,874,368-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK3). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be
initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS8161ExxD(GT/D)-xxxV operates on a 1.8 V or 2.5 V
power supply. All inputs are 1.8 V or 2.5 V compatible. Separate
output power (V
) pins are used to decouple output noise
DDQ
from the internal circuits and are 1.8 V or 2.5 Vcompatible.
Parameter Synopsis
-333
-250
-200
-150
Unit
t
3.0
3.0
3.0
4.0
3.0
5.0
3.8
6.7
ns
ns
KQ
Pipeline
3-1-1-1
tCycle
Curr (x18)
Curr (x32/x36)
305
360
245
285
205
235
175
195
mA
mA
t
5.0
5.0
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
KQ
Flow
Through
2-1-1-1
tCycle
Curr (x18)
Curr (x32/x36)
235
265
215
245
205
225
190
205
mA
mA
Rev: 1.03b 9/2013
1/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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