Datasheet > GM76C256CE

GM76C256CE

更新时间： 2022-11-26 04:14:53

品牌	Logo	应用领域
海力士 - HYNIX		静态存储器
页数	文件大小	规格书
11页	177K
描述
32K x8 bit 5.0V Low Power CMOS slow SRAM

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数据手册

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GM76C256CE 数据手册

GM76C256C Series

TIMING DIAGRAM

READ CYCLE 1

tRC

ADDR

tAA

tOE

tOH

tOLZ

tACS

tCLZ

tOHZ

tCHZ

High-Z

Data

Out

Data Valid

Note(READ CYCLE):

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and arenot

referenced to output voltage levels.

2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device

and from device to device.

3. /WE is high for the read cycle.

READ CYCLE 2

tRC

ADDR

tAA

tOH

Data

Out

Previous Data

Data Valid

Note(READ CYCLE):

1. /WE is high for the read cycle.

2. Device is continuously selected /CS= VIL.

3. /OE =VIL.

Rev 03 / Apr. 2000

1...3 4 567 8 9...11

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