GM72V66441ET/ELT
4, 194, 304 W O R D x 4 B I T x 4 B A N K
S Y N C H R O N O U S D Y N A M I C R A M
Description
Pin Configuration
T h e G M 7 2 V 6 6 4 4 1 E T / E L T i s
a s y n c h r o n o u s
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V C C
N C
V C C Q
N C
V S S
N C
V S S Q
N C
d y n a m i c r a n d o m a c c e s s m e m o r y c o m p r i s e d o f
6 7 , 1 0 8 , 8 6 4 m e m o r y c e l l s a n d l o g i c i n c l u d i n g
input and output circuits operating synchronously
by referring to the positive edge of the externally
p r o v i d e d C l o c k .
2
3
4
5
D Q 0
V S S Q
N C
D Q 3
V C C Q
N C
6
7
T h e G M 7 2 V 6 6 4 4 1 E T / E L T p r o v i d e s f o u r b a n k s
8
N C
V C C Q
N C
N C
V S S Q
N C
o f 4 , 1 9 4 , 3 0 4 w o r d b y
4 b i t t o r e a l i z e h i g h
9
b a n d w i d t h w i t h t h e C l o c k f r e q u e n c y u p t o 1 4 3
M h z .
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
D Q 1
V S S Q
N C
D Q 2
V C C Q
N C
JEDEC STANDARD
400 mil 54 PIN TSOP II
V C C
N C
V S S
N C
Features
(TOP VIEW)
/W E
D Q M
C L K
C K E
N C
* P C 1 3 3 / P C 1 0 0 / P C 6 6 C o m p a t i b l e
- 7 ( 1 4 3 M H z ) / - 7 5 ( 1 3 3 M H z ) / - 8 ( 1 2 5 M H z )
-7K(PC100, 2-2-2)/-7J(PC100, 3-2-2)
* 3. 3V single Power supply
/C A S
/R A S
/C S
B A 0 / A 1 3
B A 1 / A 1 2
A 1 0 , A P
A 0
A 1 1
A 9
* L V T T L i n t e r f a c e
A 8
* M a x C l o c k f r e q u e n c y
A 7
A 6
A 1
1 4 3 / 1 3 3 / 1 2 5 / 1 0 0 M H z
A 2
A 5
* 4 , 0 9 6 r e f r e s h c y c l e p e r 6 4 m s
* T w o k i n d s o f r e f r e s h o p e r a t i o n
Auto refresh / Self refresh
A 3
V C C
A 4
V S S
* Programmable burst access capability ;
- Sequence:Sequential / Interleave
Pin Name
C L K
C K E
C l o c k
- Length
:1/2/4/8/FP
Clock Enable
* P r o g r a m m a b l e C A S l a t e n c y : 2 / 3
* 4 Banks can operate independently or
simultaneously
C S
C h i p S e l e c t
R A S
R o w A d d r e s s S t r o b e
C o l u m n A d d r e s s S t r o b e
W r i t e E n a b l e
C A S
* Burst read/burst write or burst read/single
write operation capability
W E
A 0 ~ A 9 , A 1 1
A 1 0 / A P
B A 0 / A 1 3
~ B A 1 / A 1 2
D Q 0 ~ D Q 7
D Q M
A d d r e s s i n p u t
* I n p u t a n d o u t p u t m a s k i n g b y D Q M i n p u t
* O n e C l o c k o f b a c k t o b a c k r e a d o r w r i t e
c o m m a n d i n t e r v a l
Address input or Auto P r e c h a r g e
Bank select
* S y n c h r o n o u s P o w e r d o w n a n d C l o c k
s u s p e n d c a p a b i l i t y w i t h o n e C l o c k l a t e n c y
for both entry and exit
Data input / Data output
Data input / output Mask
V C C f o r D Q
V C C Q
V S S Q
* J E D E C S t a n d a r d 5 4 P i n 4 0 0 m i l T S O P I I P a c k a g e
V S S f o r D Q
V C C
Power for internal circuit
Ground for internal circuit
N o C o n n e c t i o n
V S S
N C
This document is a general product description and is subject to change without notice. H y n i x s e m i c o n d u c t o r d o e s n o t a s s u m e a n y
-1-
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1. 1/Apr. 01