Datasheet > GM72V66841GLT-S

GM72V66841GLT-S

更新时间： 2024-02-14 05:29:18

品牌	Logo	应用领域
海力士 - HYNIX		时钟动态存储器光电二极管内存集成电路
页数	文件大小	规格书
11页	49K
描述
Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54

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技术参数
数据手册

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GM72V66841GLT-S 技术参数

生命周期：	Obsolete	包装说明：	TSOP, TSOP54,.46,32
Reach Compliance Code：	compliant	风险等级：	5.84
最长访问时间：	6 ns	最大时钟频率 (fCLK)：	100 MHz
I/O 类型：	COMMON	交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PDSO-G54	内存密度：	67108864 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	8
端子数量：	54	字数：	8388608 words
字数代码：	8000000	最高工作温度：	70 °C
最低工作温度：		组织：	8MX8
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP	封装等效代码：	TSOP54,.46,32
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
电源：	3.3 V	认证状态：	Not Qualified
刷新周期：	4096	连续突发长度：	1,2,4,8,FP
最大待机电流：	0.002 A	子类别：	DRAMs
最大压摆率：	0.12 mA	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	DUAL
Base Number Matches：	1

GM72V66841GLT-S 数据手册

GM72V66841G

4 Banks x 2M x 8Bit Synchronous DRAM

DESCRIPTION

The Hyundai GM72V66841G is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. GM72V66841G is organized as 4banks of 2,097,152x8.

GM72V66841G is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read

or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of sys-

tem clock

•

Data mask function by DQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

GM72V66841GT-5/55/67

GM72V66841GT-K

200/183/166/143MHz

133MHz

GM72V66841GT-H

GM72V66841GT-P

133MHz

Normal

100MHz

GM72V66841GT-S

100MHz

4Banks x 2Mbits x8

LVTTL

400mil 54pin TSOP II

GM72V66841GLT-5/55/6/7

GM72V66841GLT-K

GM72V66841GLT-H

GM72V66841GLT-P

GM72V66841GLT-S

200/183/166/143MHz

133MHz

Low power

100MHz

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use

of circuits described. No patent licenses are implied.

Rev. 0.2/Oct.00

12 3 4 5 6 7...11

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