Datasheet > GM71V17403CL-7

GM71V17403CL-7

更新时间： 2022-11-27 17:36:27

品牌	Logo	应用领域
海力士 - HYNIX		/
页数	文件大小	规格书
10页	101K
描述
4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM

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数据手册

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GM71V17403CL-7 数据手册

GM71V17403C

GM71VS17403CL

Capacitance (VCC = 3.3V +/- 0.3V, TA = 25C)

Symbol

CI1

Parameter

Input Capacitance (Address)

Input Capacitance (Clocks)

Output Capacitance (Data-In/Out)

Min

Max

Unit

Note

CI2

CI/O

1, 2

Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. CAS = VIH to disable DOUT

AC Characteristics (VCC = 3.3V +/- 0.3V, VSS = 0V, TA = 0 ~ 70C, Notes 1, 2, 18)

Test Conditions

Input rise and fall times : 2ns

Input levels : VIL = 0V, VIH = 3V

Input timing reference levels : 0.8V, 2.0V

Output timing reference levels : 0.8V, 2.0V

Output load : 1 TTL gate + C (100pF)

(Including scope and jig)

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

GM71V(S)17403 GM71V(S)17403 GM71V(S)17403

C/CL-5 C/CL-6 C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

Random Read or Write Cycle Time

RAS Precharge Time

104

124

tRP

CAS Precharge Time

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

RSH

CSH

CRP

ODD

DZO

DZC

RAS Pulse Width

50 10,000

10,000

CAS Pulse Width

8 10,000 10 10,000

13 10,000

Row Address Set up Time

Row Address Hold Time

Column Address Set-up Time

Column Address Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time

RAS Hold Time

12 37

10 25

14 45

12 30

14 52

12 35

CAS Hold Time

CAS to RAS Precharge Time

OE to DIN Delay Time

OE Delay Time from DIN

CAS Delay Time from DIN

Transition Time (Rise and Fall)

Rev 0.1 / Apr’01

1 2 345 6 7...10

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