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GD14515-68BA PDF预览

GD14515-68BA

更新时间： 2024-01-04 08:09:56
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
8页 129K
描述
SMPTE

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GD14515-68BA 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：QFP, QFP68,.85SQ,40Reach Compliance Code：unknown
风险等级：5.78商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：S-XQFP-G68JESD-609代码：e0
端子数量：68最高工作温度：70 °C
最低工作温度：封装主体材料：CERAMIC
封装代码：QFP封装等效代码：QFP68,.85SQ,40
封装形状：SQUARE封装形式：FLATPACK
电源：3.3,5 V认证状态：Not Qualified
子类别：Other Consumer ICs表面贴装：YES
技术：BIPOLAR温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1 mm端子位置：QUAD
Base Number Matches：1

GD14515-68BA 数据手册

 浏览型号GD14515-68BA的Datasheet PDF文件第2页浏览型号GD14515-68BA的Datasheet PDF文件第3页浏览型号GD14515-68BA的Datasheet PDF文件第4页浏览型号GD14515-68BA的Datasheet PDF文件第5页浏览型号GD14515-68BA的Datasheet PDF文件第6页浏览型号GD14515-68BA的Datasheet PDF文件第7页 
HDTV  
Serialiser  
GD14515  
Preliminary  
General Information  
Features  
l
The GD14515 High Definition TV  
Serialiser is designed for point-to-point  
serial transmission systems for HDTV  
signals according to SMPTE292.  
The VCO centre frequency is determined  
by the REFCK multiplied by 20. The loop  
filter time constant is determined by an  
external RC filter, allowing the user to  
control the loop characteristics.  
Nominal data-rate 1485 Mbit/s NRZI.  
l
Two operating ranges:  
–
–
1.2 -1.5 Gbit/s  
300 - 375 Mbit/s  
The device provides a fully integrated  
solution for:  
l
l
l
l
The multiplexed data stream is output by  
two independent Open Collector 75 Ω  
cable drivers each with a sink capability  
of 30 mA. The cable driver current may  
be adjusted in the range 20 mA - 30 mA  
by the current control pin (CIN). The out-  
put can be configured as a 50 Ω differen-  
tial PECL output to drive an optical  
transmitter module.  
Jitter in accordance with SMPTE292.  
Complete Clock Multiplier on-chip.  
PLL Lock Detect Output.  
u
a 1485 Mbit/s transmitter with on-chip  
clock multiplying Phase Lock Loop  
u
20:1 MUX  
Scrambler  
u
u
NRZI encoder  
Cable driver.  
u
Two independent differential Open  
Collector 75 Ω cable drivers with  
external termination resistors.  
GD14515 multiplexes a 20 bit parallel  
interface into a single output data stream,  
using a separate reference clock or the  
clock following the 20 bit data.  
l
l
l
The GD14515 is packaged in a 68 pin  
leaded Multi Layer Ceramic (MLC) pack-  
age with cavity down for easy cooling.  
Supply operation: 5 V and 3.3 V.  
Power dissipation: 1.2 W typ.  
The on-chip PLL circuit provides internal  
clock synchronisation and consists of:  
68 pin Multi Layer Ceramic (MLC)  
leaded package with transmission  
lines.  
u
a Phase/Frequency Comparator  
a Lock Detect Circuit  
u
u
a Tristateable Charge Pump  
a wide tuning range VCO.  
u
PAR  
SEN  
NEN  
Applications  
SOP1  
SON1  
CIP1  
l
HDTV Studio equipment.  
DIN0  
SOP2  
DIN19  
MUX  
Scramble  
NRZI  
Phase  
Ctrl.  
CPH0  
CPH1  
LD  
SON2  
CIP2  
TCKEN  
TCK  
TCKN  
/20  
Clock  
Divide  
VCO  
/4  
Divide  
CKOUT  
VEE  
VCTL  
DEN  
V
R
U
U
V3V3  
V3V3A  
PFC  
D
D
VCC  
VCCO  
VCCA  
REFCK  
REFCN  
NLDET  
PFCO  
12345678

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