Datasheet > GD14526-40BA

GD14526-40BA

更新时间： 2024-02-06 01:20:36

品牌	Logo	应用领域
英特尔 - INTEL		商用集成电路
页数	文件大小	规格书
8页	191K
描述
Consumer Circuit, CQFP40,

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技术参数
数据手册

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GD14526-40BA 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	QFF, QFL40,.68SQ,40	Reach Compliance Code：	compliant
风险等级：	5.37	Is Samacsys：	N
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	S-XQFP-F40
JESD-609代码：	e0	端子数量：	40
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	CERAMIC	封装代码：	QFF
封装等效代码：	QFL40,.68SQ,40	封装形状：	SQUARE
封装形式：	FLATPACK	电源：	3.3,5 V
认证状态：	Not Qualified	子类别：	Other Consumer ICs
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	FLAT
端子节距：	1 mm	端子位置：	QUAD
Base Number Matches：	1

GD14526-40BA 数据手册

HDTV

1.5 Gbit/s

Re-timer

GD14526

Preliminary

General Information

Features

The GD14526 Re-timer is designed for

1.2 Gbit/s - 1.5 Gbit/s point-to-point serial

transmission systems such as HDTV sig-

nals according to SMPTE292. Alterna-

tively the GD14526 can be configured to

operate in the 300 Mbit/s - 375 Mbit/s

range.

When in lock, the digital Lock Detect

Circuit (LDC) uses the incoming data to

control the PLL. When not in lock, i.e. the

VCO frequency is more than 500 ppm

away from the REFCK frequency, the

LDC switches to the local clock (REFCK)

until the VCO frequency once more en-

ters the ±500 ppm range. Then it

switches back to the PD, comparing the

VCO clock to the incoming data stream.

The LDC continuously monitors the VCO

frequency against the REFCK input,

clearing LOCK if the VCO leaves the lock

range.

Two operating ranges:

–

1.2 -1.5 Gbit/s

300 - 375 Mbit/s

Jitter in accordance with SMPTE292.

High-speed data input and output use

Loop-through bondings to reduce

reflections.

The device provides a fully integrated so-

lution for Clock Recovery and Data

(CDR) Re-timing and includes an output

driver for 50/75 S cables. The CDR can

be bypassed for data rates outside the

VCO range.

Complete Clock/20, Data Recovery,

and Lock Acquisition on one IC.

Digitally controlled capture and lock.

–

Full capture range with true

Phase/Frequency detect between

VCO-CLK and REFCK.

The Clock and Data Recovery circuit

consists of:

The high-speed data input is differential

and compatible with PECL levels. It is

connected via loop-through transmission

lines to minimise stub related reflections.

The open collector cable driver has dif-

ferential outputs and the current in the

output stage can be adjusted to a maxi-

mum of 36 mA.

a Bang-Bang Phase Detector (PD)

with data re-timing

a Phase-Frequency Comparator

(PFC)

a Lock Detect Circuit (LDC) with

Lock Alarm Output

–

Bang-Bang Phase Detector

between VCO-CLK and DATA.

Lock in range ±500 ppm or

±2000 ppm referred to REFCK.

Lock Alarm Output.

a Tristatable Charge Pump

a wide tuning range VCO.

Re-timed differential 50/75 S cable

driver output with external termination

resistors.

The GD14526 is packaged in a 40 pin

leaded Multi Layer Ceramic (MLC) pack-

age with cavity down for easy cooling.

The VCO centre frequency is determined

by the REFCK multiplied by 20. The loop

filter time constant is determined by an

external RC filter.

Supply operation: 5 V and 3.3 V.

Power dissipation: 1100 mW typ.

Power down mode for bypass

operation.

SOP

SIP

SIN

40 pin Multi Layer Ceramic (MLC)

leaded package with transmission

lines.

SON

CIP

VCC_CDR

DEN

Bang

VCO

VEE

Div.

Phase

Detector

VCTL

V3V3

V3V3A

Applications

VCCA

VCCD

VCCO

Charge

Pump

HDTV Studio equipment.

Gigabit Ethernet

/20

Clock

Divide

Lock

Detect

4:2

MUX

PFC

OUTCHP

SEL0

SEL1

LOCK

REFCK

CKOUT

12 3 4 5 6 7 8

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