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FT18/TG PDF预览

FT18/TG

更新时间: 2024-01-31 12:20:34
品牌 Logo 应用领域
恩智浦 - NXP 传感器图像传感器
页数 文件大小 规格书
16页 235K
描述
Frame Transfer CCD Image Sensor

FT18/TG 技术参数

生命周期:ActiveReach Compliance Code:unknown
风险等级:5.56其他特性:SENSITIVITY IS 5.8 KEL/LUX, ELECTRONIC SHUTTER
阵列类型:FRAME TRANSFER主体宽度:15.49 mm
主体高度:4.53 mm主体长度或直径:29.7 mm
数据速率:40 Mbps动态范围:63.8 dB
水平像素:1024外壳:CERAMIC
安装特点:THROUGH HOLE MOUNT光学格式:2/3 inch
输出类型:ANALOG VOLTAGE封装形状/形式:RECTANGULAR
像素大小:7.5X7.5 µm传感器/换能器类型:IMAGE SENSOR,CCD
最大供电电压:24 V最小供电电压:16 V
表面贴装:NO端接类型:SOLDER
垂直像素:1024Base Number Matches:1

FT18/TG 数据手册

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Philips Semiconductors  
Product specification  
Frame Transfer CCD Image Sensor  
FT 18  
Architecture of the FT 18  
The FT18 consists of a shielded storage section and an open image  
section. Both sections have the same structure with identical cells  
and properties. The only difference between the two sections is the  
optical light shield.  
The storage section is controlled by four storage clocks (B1 to B4).  
An output register is located below the storage section for read-out.  
The output register has buffers at both ends.This allows either normal  
or mirrored read-out.  
The optical centres of all pixels in the image section form a square  
grid. The charge is generated and integrated in this section. The  
image section is controlled by four image clocks (A1 to A4). After  
integration, the image charge is completely shifted to the storage  
section. The integration time is electronically controlled by charge  
reset (CR).  
Transport of the pixels in the output register is controlled by three  
register clock phases (C1 to C3).The register can be used for vertical  
binning. Horizontal binning can be achieved by summing pixel  
charges under the floating diffusion. More information can be found  
in the application note.Figure 2 shows the detailed internal structure.  
IMAGE SECTION  
10.9 mm  
1:1  
Image diagonal  
Aspect ratio  
Active image width x height  
Total width x height  
7.680 x 7.680 mm2  
8.040 x 7.860 mm2  
7.5 x 7.5 µm2  
100%  
Pixel width x height  
Geometric fill factor  
Image clock pins  
A1, A2, A3, A4  
<3.75nF per pin  
1024  
Capacity of each clock phase  
Number of active lines  
Number of contour lines  
Number of black lines  
4 (top) + 1 (bottom)  
8 (top) + 11 (bottom)  
1048  
Total number of lines  
Number of active pixels per line  
Number of overscan (timing) pixels per line  
Number of black reference pixels per line  
Total number of pixels per line  
1024  
8 (2x4)  
40 (2x20)  
1072  
STORAGE SECTION  
Storage width x height  
8.040 x 7.860 mm2  
Cell width x height  
7.5 x 7.5 µm2  
B1, B2, B3, B4  
<4.1nF per pin  
1072 x 1048  
Storage clock phases  
Capacity of each B phase  
Number of cells per line x number of lines  
OUTPUT REGISTER  
Output buffers (three-stage source follower)  
Number of registers  
2
1 (bidirectional below storage)  
Number of register cells below storage  
Number of extra cells to output  
1072  
2 x 7  
Output register horizontal transport clock pins  
Capacity of each C-clock phase  
Overlap capacity between neighbouring C-clocks  
Reset Gate clock phases  
3 (C1..C3)  
<85pF per pin  
<35pF  
2 pins (RGL, RGR)  
<15pF  
Capacity of each RG  
2000 January  
3

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