Datasheet > FMS3110KRC

FMS3110KRC

更新时间： 2024-02-12 21:00:16

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		转换器
页数	文件大小	规格书
11页	173K
描述
Triple Video D/A Converters 3 x 10 bit, 150 Ms/s

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技术参数
数据手册

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FMS3110KRC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LFQFP, QFP48,.35SQ,20
针数：	48	Reach Compliance Code：	compliant
风险等级：	5.81	最大模拟输出电压：	1.5 V
最小模拟输出电压：	-0.4 V	转换器类型：	D/A CONVERTER
输入位码：	BINARY	输入格式：	PARALLEL, WORD
JESD-30 代码：	S-PQFP-G48	JESD-609代码：	e3
长度：	7 mm	最大线性误差 (EL)：	0.25%
湿度敏感等级：	3	位数：	10
功能数量：	1	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP48,.35SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Other Converters
最大压摆率：	125 mA	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin (Sn)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm	Base Number Matches：	1

FMS3110KRC 数据手册

FMS3110/3115

PRODUCT SPECIFICATION

D/A Outputs

Functional Description

Each D/A output is a current source. To obtain a voltage

output, a resistor must be connected to ground. Output

voltage depends upon this external resistor, the reference

voltage, and the value of the gain-setting resistor connected

Within the FMS3110/3115 are three identical 10-bit D/A

converters, each with a current source output. External loads

are required to convert the current to voltage outputs. Data

inputs RGB are overridden by the BLANK input. SYNC

7-0

between R

and GND.

REF

= H activates, sync current from I for sync-on-green video

signals.

Normally, a source termination resistor of 75 Ohms is

connected between the D/A current output pin and GND

near the D/A converter. A 75 Ohm line may then be

connected with another 75 Ohm termination resistor at the

far end of the cable. This “double termination” presents the

D/A converter with a net resistive load of 37.5 Ohms.

Digital Inputs

All digital inputs are TTL-compatible. Data is registered on

the rising edge of the CLK signal. Following one stage of

pipeline delay, the analog output changes t

edge of CLK.

after the rising

The FMS3110/3115 may also be operated with a single 75

Ohm terminating resistor. To lower the output voltage swing

to the desired range, the nominal value of the resistor on

SYNC and BLANK

SYNC and BLANK inputs control the output level (Figure 1

and Table 1) of the D/A converters during CRT retrace

intervals. BLANK forces the D/A outputs to the blanking

level while SYNC = L turns off a current source that is

connected to the green D/A converter. SYNC = H adds a 40

IRE sync pulse to the green output, SYNC = L sets the green

output to 0.0 Volts during the sync tip. SYNC and BLANK

are registered on the rising edge of CLK.

should be doubled.

REF

Voltage Reference

All three D/A converters are supplied with a common

voltage reference. Internal bandgap voltage reference voltage

is +1.235 Volts with a 3KΩ source resistance. An external

voltage reference may be connected to the V

overriding the internal voltage reference.

pin,

REF

BLANK gates the D/A inputs and sets the pedestal voltage.

If BLANK = HIGH, the D/A inputs are added to a pedestal

which offsets the current output. If BLANK = Low, data

inputs and the pedestal are disabled.

A 0.1µF capacitor must be connected between the COMP

pin and V to stabilize internal bias circuitry and ensure

low-noise operation.

Power and Ground

Required power is a single +5.0 Volt supply. To minimize

power supply induced noise, analog +5V should be connected

data: 660 mV max.

to V

pins with 0.1 and 0.01 µF decoupling capacitors

pin or pin pair.

placed adjacent to each V

pedestal: 54 mV

sync: 286 mV

The high slew-rate of digital data makes capacitive coupling

to the outputs of any D/A converter a potential problem.

Since the digital signals contain high-frequency components

of the CLK signal, as well as the video output signal, the

resulting data feedthrough often looks like harmonic

distortion or reduced signal-to-noise performance. All

ground pins should be connected to a common solid ground

plane for best performance.

Figure 1. Nominal Output Levels

REV. 1.05 12/21/00

123 4 5 6 7...11

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