Datasheet > FM93C46ATEMT8

FM93C46ATEMT8

更新时间： 2024-01-19 10:32:54

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数	文件大小	规格书
13页	116K
描述
EEPROM, 64X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

FM93C46ATEMT8 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	TSSOP, TSSOP8,.25
针数：	8	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.51
风险等级：	5.75	Is Samacsys：	N
其他特性：	DATA RETENTION = 40 YEARS	备用内存宽度：	8
最大时钟频率 (fCLK)：	1 MHz	数据保留时间-最小值：	40
耐久性：	1000000 Write/Erase Cycles	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0	长度：	4.4 mm
内存密度：	1024 bit	内存集成电路类型：	EEPROM
内存宽度：	16	功能数量：	1
端子数量：	8	字数：	64 words
字数代码：	64	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	64X16	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行：	SERIAL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	串行总线类型：	MICROWIRE
最大待机电流：	0.00005 A	子类别：	EEPROMs
最大压摆率：	0.001 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm	最长写入周期时间 (tWC)：	10 ms
写保护：	SOFTWARE	Base Number Matches：	1

FM93C46ATEMT8 数据手册

2. After inputting the last bit of data (A0 bit), CS signal must be

broughtlowbeforethenextrisingedgeoftheSKclock. Thisfalling

edge of the CS initiates the self-timed programming cycle. It takes

t_WPtime (Refer appropriate DC and AC Electrical Characteristics

table)fortheinternalprogrammingcycletofinish.Duringthistime,

the device remains busy and is not ready for another instruction.

Status of the internal programming can be polled as described

under WRITE instruction description. While the device is busy, it

is recommended that no new instruction be issued. Refer Erase

All cycle diagram.

5) Write Disable (WDS)

Write Disable (WDS) instruction disables all programming opera-

tions and should follow all programming operations. Executing

this instruction after a valid write instruction would protect against

accidental data disturb due to spurious noise, glitches, inadvert-

ent writes etc. Input information (Start bit, Opcode and Address)

for this WDS instruction should be issued as listed under Table 1

or Table 2. The device becomes write-disabled at the end of this

cycle when the CS signal is brought low. Execution of a READ

instructionisindependentofWDSinstruction. ReferWriteDisable

cycle diagram.

Note: The Fairchild CMOS EEPROMs do not require an “ERASE” or “ERASE ALL”

instruction prior to the “WRITE” or “WRITE ALL” instruction, respectively. The

“ERASE” and “ERASE ALL” instructions are included to maintain compatibility with

earlier technology EEPROMs.

6) Erase (ERASE)

The ERASE instruction will program all bits in the specified

location to logical “1” state. Input information (Start bit, Opcode

and Address) for this WDS instruction should be issued as listed

under Table 1 or Table 2. After inputting the last bit of data (A0 bit),

CS signal must be brought low before the next rising edge of the

SK clock. This falling edge of the CS initiates the self-timed

programming cycle. It takes t_WPtime (Refer appropriate DC and

AC Electrical Characteristics table) for the internal programming

cycle to finish. During this time, the device remains busy and is not

ready for another instruction. Status of the internal programming

can be polled as described under WRITE instruction description.

While the device is busy, it is recommended that no new instruc-

tion be issued. Refer Erase cycle diagram.

Clearing of Ready/Busy status

When programming is in progress, the Data-Out pin will display

the programming status as either BUSY (low) or READY (high)

when CS is brought high (DO output will be tri-stated when CS is

low). To restate, during programming, the CS pin may be brought

high and low any number of times to view the programming status

without affecting the programming operation. Once programming

is completed (Output in READY state), the output is ‘cleared’

(returned to normal tri-state condition) by clocking in a Start Bit.

After the Start Bit is clocked in, the output will return to a tri-stated

condition. When clocked in, this Start Bit can be the first bit in a

command string, or CS can be brought low again to reset all

internal circuits. Refer Clearing Ready Status diagram.

7) Erase All (ERAL)

与FM93C46ATEMT8相关器件

型号	品牌	描述	获取价格	数据表
FM93C46ATEN	FAIRCHILD	EEPROM, 64X16, Serial, CMOS, PDIP8, PLASTIC, DIP-8	获取价格
FM93C46ATLEM8	FAIRCHILD	EEPROM, 64X16, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, SO-8	获取价格
FM93C46ATLEM8X	FAIRCHILD	EEPROM, 64X16, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, SO-8	获取价格
FM93C46ATLEMT8	FAIRCHILD	EEPROM, 64X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8	获取价格
FM93C46ATLEMT8X	FAIRCHILD	EEPROM, 64X16, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8	获取价格
FM93C46ATLEN	FAIRCHILD	EEPROM, 64X16, Serial, CMOS, PDIP8, PLASTIC, DIP-8	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

FM93C46ATEMT8

FM93C46ATEMT8 技术参数

FM93C46ATEMT8 数据手册

与FM93C46ATEMT8相关器件

与FM93C46ATEMT8相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

FM93C46ATEMT8

FM93C46ATEMT8 技术参数

FM93C46ATEMT8 数据手册

与FM93C46ATEMT8相关器件

与FM93C46ATEMT8相关文章

您还可以找

您在本页遇到什么问题？