Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
-65°C to +150°C
Ambient Operating Temperature
FM93C46AL/LZ
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
FM93C46ALE/LZE
FM93C46ALV/LZV
Lead Temperature
(Soldering, 10 sec.)
+300°C
Power Supply (VCC
)
2.7V to 5.5V
ESD rating
2000V
DC and AC Electrical Characteristics VCC = 2.7V to 4.5V unless otherwise specified. Refer to
page 3 for VCC = 4.5V to 5.5V
Symbol
ICCA
Parameter
Conditions
CS = VIH, SK=250 KHz
CS = VIL
Min
Max
Units
Operating Current
1
mA
ICCS
Standby Current
L
LZ (2.7V to 4.5V)
10
1
µA
µA
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
1
µA
IILO
Input Leakage ORG Pin
ORG tied to VCC
ORG tied to VSS (Note 3)
-1
-2.5
1
2.5
µA
VIL
VIH
Input Low Voltage
Input High Voltage
-0.1
0.8VCC
0.15VCC
VCC +1
V
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10µA
IOH = -10µA
0.1VCC
0.9VCC
fSK
tSKH
tSKL
SK Clock Frequency
SK High Time
(Note 4)
0
1
1
250
KHz
µs
µs
SK Low Time
tCS
Minimum CS Low Time
(Note 5)
1
µs
tCSS
tDH
CS Setup Time
DO Hold Time
DI Setup Time
0.2
70
µs
ns
µs
tDIS
0.4
tCSH
tDIH
tPD
CS Hold Time
DI Hold Time
Output Delay
0
ns
µs
µs
0.4
2
1
tSV
CS to Status Valid
µs
tDF
CS to DO in Hi-Z
Write Cycle Time
CS = VIL
0.4
15
µs
ms
tWP
Note 1: Stressabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanentdamage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditionsabovethoseindicatedintheoperationalsectionsofthespecificationisnotimplied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance TA = 25°C, f = 1 MHz or
250 KHz (Note 6)
Note 2: Typical leakage values are in the 20nA range.
Note 3: ORG pin may draw >1µA when in x8 mode due to the internal pull-up transistor.
Symbol
Test
Typ Max Units
Note 4: TheshortestallowableSKclockperiod=1/fSK (asshownunderthefSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
COUT
CIN
Output Capacitance
Input Capacitance
5
5
pF
pF
Note 5: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 6: This parameter is periodically sampled and not 100% tested.
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
0.3V/1.8V
VIL/VIH
VOL/VOH
Timing Level
0.8V/1.5V
IOL/IOH
Timing Level
2.7V ≤ VCC ≤ 5.5V
1.0V
10µA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
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FM93C46A Rev. C.1