December 2001
FM24C128 – 128K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
Features
FM24C128 is a 128Kbit CMOS non-volatile serial EEPROM
organized as 16K x 8 bit memory. This device confirms to
Extended IIC 2-wire protocol that allows accessing of memory in
excessof16KbitonanIICbus.Thisserialcommunicationprotocol
uses a Clock signal (SCL) and a Data signal (SDA) to synchro-
nously clock data between a master (e.g. a microcontroller) and a
slave (EEPROM). FM24C128 is designed to minimize pin count
and simplify PC board layout requirements.
I Extended operating voltage: 2.5V to 5.5V
I Up to 400 KHz clock frequency at 2.5V to 5.5V
I Low power consumption
—0.5mA active current typical
—10µA standby current typical
—1µA standby current typical (L version)
—0.1µA standby current typical (LZ version)
I Schmitt trigger inputs
FM24C128 offers hardware write protection where by the entire
I 64 byte page write mode
memoryarraycanbewriteprotectedbyconnectingWPpintoVCC
The entire memory then becomes unalterable until the WP pin is
switched to VSS
.
I Self timed write cycle (6ms max)
I Hardware Write Protection for the entire array
I Endurance: up to 100K data changes
I Data Retention: Greater than 40 years
I Packages: 8-Pin DIP, 8-Pin SO and 8-Pin TSSOP
.
“LZ” and “L” versions of FM24C128 offer very low standby current
making them suitable for low power applications. This device is
offered in SO, TSSOP and DIP packages.
Fairchild EEPROMs are designed and tested for applications
requiringhighendurance, highreliabilityandlowpowerconsump-
tion.
I Temperature range
—Commercial: 0°C to +70°C
—Industrial (E): -40°C to +85°C
—Automotive (V): -40°C to +125°C
Block Diagram
V
SS
WRITE
LOCKOUT
V
CC
H.V. GENERATION
TIMING &CONTROL
WP
START
STOP
SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
2
E
PROM
ARRAY
XDEC
SCL
A2
A1
A0
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
D
OUT
DATA REGISTER
D
IN
1
© 2001 Fairchild Semiconductor Corporation
FM24C128 Rev. D
www.fairchildsemi.com