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FDMF6707B PDF预览

FDMF6707B

更新时间: 2024-01-01 02:36:52
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 服务器主板节能技术
页数 文件大小 规格书
18页 1493K
描述
Extra-Small, High-Performance, High- Frequency DrMOS Module

FDMF6707B 数据手册

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Skip Mode (SMOD#)  
The SMOD function allows for higher converter  
efficiency under light-load conditions. During SMOD, the  
low-side FET gate signal is disabled (held LOW),  
preventing discharging of the output capacitors as the  
filter inductor current attempts reverse current flow –  
also known as “Diode Emulation” Mode.  
Table 2. SMOD# Logic  
DISB#  
PWM  
SMOD#  
GH  
0
GL  
0
0
1
1
1
1
1
X
X
X
0
0
1
1
3-State  
0
0
0
1
0
1
0
0
When the SMOD# pin is pulled HIGH, the synchronous  
buck converter works in Synchronous Mode. This mode  
allows for gating on the low-side FET. When the  
SMOD# pin is pulled LOW, the low-side FET is gated  
off. If the SMOD# pin is connected to the PWM  
controller, the controller can actively enable or disable  
SMOD when the controller detects light-load condition  
from output current sensing. This pin is active LOW.  
See Figure 26 for timing delays.  
1
0
0
1
1
0
Note:  
4. The SMOD feature is intended to have low  
propagation delay between the SMOD signal and  
the low-side FET VGS response time to control  
diode emulation on a cycle-by-cycle basis.  
SMOD#  
VIH_SMOD  
VIL_SMOD  
VIH_PWM  
VIH_PWM  
VIL_PWM  
PWM  
90%  
GH  
to  
VSWH  
10%  
10%  
DCM  
VOUT  
CCM  
CCM  
2.2V  
VSWH  
GL  
90%  
1.0V  
10%  
10%  
tPD_PLGHL  
tPD_PHGLL  
tPD_PHGHH  
tPD_SHGLH  
tPD_SLGLL  
tD_DEADOFF  
tD_DEADON  
Delay from SMOD# going  
LOW to LS VGS LOW  
Delay from SMOD# going  
HIGH to LS V HIGH  
GS  
HS turn -on with SMOD# LOW  
Figure 26. SMOD# Timing Diagram  
© 2011 Fairchild Semiconductor Corporation  
FDMF6707B • Rev. 1.0.2  
www.fairchildsemi.com  
13  

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