FDMF6707B

更新时间： 2024-01-01 02:36:52

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		服务器主板节能技术
页数	文件大小	规格书
18页	1493K
描述
Extra-Small, High-Performance, High- Frequency DrMOS Module

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数据手册

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FDMF6707B 数据手册

Skip Mode (SMOD#)

The SMOD function allows for higher converter

efficiency under light-load conditions. During SMOD, the

low-side FET gate signal is disabled (held LOW),

preventing discharging of the output capacitors as the

filter inductor current attempts reverse current flow –

also known as “Diode Emulation” Mode.

Table 2. SMOD# Logic

DISB#

PWM

SMOD#

3-State

When the SMOD# pin is pulled HIGH, the synchronous

buck converter works in Synchronous Mode. This mode

allows for gating on the low-side FET. When the

SMOD# pin is pulled LOW, the low-side FET is gated

off. If the SMOD# pin is connected to the PWM

controller, the controller can actively enable or disable

SMOD when the controller detects light-load condition

from output current sensing. This pin is active LOW.

See Figure 26 for timing delays.

Note:

4. The SMOD feature is intended to have low

propagation delay between the SMOD signal and

the low-side FET VGS response time to control

diode emulation on a cycle-by-cycle basis.

SMOD#

V_{IH_SMOD}

V_{IL_SMOD}

V_{IH_PWM}

V_{IL_PWM}

PWM

90%

VSWH

10%

DCM

V_OUT

CCM

2.2V

VSWH

90%

1.0V

10%

t_{PD_PLGHL}

t_{PD_PHGLL}

t_{PD_PHGHH}

t_{PD_SHGLH}

t_{PD_SLGLL}

t_{D_DEADOFF}

t_{D_DEADON}

Delay from SMOD# going

LOW to LS V_GSLOW

Delay from SMOD# going

HIGH to LS V HIGH

HS turn -on with SMOD# LOW

Figure 26. SMOD# Timing Diagram

FDMF6707B • Rev. 1.0.2

www.fairchildsemi.com

1...10 11 121314 15 16...18

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