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EX64-FTQ128PP PDF预览

EX64-FTQ128PP

更新时间: 2024-02-27 08:23:49
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
36页 307K
描述
eX Family FPGAs

EX64-FTQ128PP 数据手册

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v3.0  
eX Family FPGAs  
Leading Edge Performance  
• 240 MHz System Performance  
• Individual Output Slew Rate Control  
• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V  
Input Tolerance and 5.0V Drive Strength  
• Software Design Support with Actel Designer Series and  
Libero Tools  
• 3.9ns Clock-to-Out (Pad-to-Pad)  
• 350 MHz Internal Performance  
Specifications  
• Up to 100% Resource Utilization with 100% Pin Locking  
• Deterministic Timing  
• 3,000 to 12,000 Available System Gates  
• As Many as 512 Maximum Flip-Flops (Using CC Macros)  
• 0.22µ CMOS Process Technology  
• Unique In-System Diagnostic and Verification Capability  
with Silicon Explorer II  
• Up to 132 User-Programmable I/O Pins  
• Boundary Scan Testing in Compliance with IEEE Standard  
1149.1 (JTAG)  
Features  
• Secure Programming Technology Prevents Reverse  
Engineering and Design Theft  
• High-Performance, Low-Power Antifuse FPGA  
• LP/Sleep Mode for Additional Power Savings  
• Advanced Small-footprint Packages  
• Hot-Swap Compliant I/Os  
General Description  
The eX family of FPGAs is a low-cost solution for low-power,  
high-performance designs. The inherent low power  
attributes of the antifuse technology, coupled with an  
additional low static power mode, make these devices ideal  
for power-sensitive applications. Fabricated with an  
advanced 0.22µ CMOS antifuse technology, these devices  
achieve high performance with no power penalty.  
• Single-Chip Solution  
• Nonvolatile  
• Live on power up  
• Power-Up/Down Friendly (No Sequencing Required for  
Supply Voltages)  
• Configurable Weak-Resistor Pull-Up or Pull-Down for  
Tristated Outputs during Power Up  
eX Product Profile  
Device  
eX64  
eX128  
eX256  
Capacity  
System Gates  
Typical Gates  
3,000  
2,000  
6,000  
4,000  
12,000  
8,000  
Register Cells (Dedicated Flip-Flops)  
Combinatorial Cells  
64  
128  
84  
128  
256  
256  
512  
Maximum User I/Os  
100  
132  
Speed Grades  
F, Std, –P  
C, I  
F, Std, –P  
C, I  
F, Std, –P  
C, I  
Temperature Grades  
Package (by pin count)  
TQFP  
CSP  
64, 100  
49, 128  
64, 100  
49, 128  
100  
128, 180  
December 2001  
1
© 2001 Actel Corporation  

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