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EX64-FTQ100I PDF预览

EX64-FTQ100I

更新时间: 2024-01-21 01:34:37
品牌 Logo 应用领域
ACTEL 现场可编程门阵列可编程逻辑时钟
页数 文件大小 规格书
44页 384K
描述
eX Automotive Family FPGAs

EX64-FTQ100I 技术参数

是否Rohs认证:不符合生命周期:Active
包装说明:QFP, QFP100,.63SQ,20Reach Compliance Code:unknown
风险等级:5.87Is Samacsys:N
最大时钟频率:178 MHzJESD-30 代码:S-PQFP-G100
输入次数:53逻辑单元数量:192
输出次数:53端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK电源:2.5,2.5/5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
子类别:Field Programmable Gate Arrays表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUADBase Number Matches:1

EX64-FTQ100I 数据手册

 浏览型号EX64-FTQ100I的Datasheet PDF文件第2页浏览型号EX64-FTQ100I的Datasheet PDF文件第3页浏览型号EX64-FTQ100I的Datasheet PDF文件第4页浏览型号EX64-FTQ100I的Datasheet PDF文件第5页浏览型号EX64-FTQ100I的Datasheet PDF文件第6页浏览型号EX64-FTQ100I的Datasheet PDF文件第7页 
v3.2  
eX Automotive Family FPGAs  
u
e
No Power-Up/Down Sequence Required for Supply  
Voltages  
Configurable Weak Resistor Pull-Up or Pull-Down  
for Tristated Outputs during Power-Up  
Individual Output Slew-Rate Control  
2.5 V and 3.3 V I/Os  
Software Design Support with Actel Designer and  
Libero® Integrated Design Environment (IDE)  
Tools  
Up to 100% Resource Utilization with 100% Pin  
Locking  
Specifications  
3,000 to 12,000 Available System Gates  
Maximum 512 Flip-Flops (Using CC Macros)  
0.22 µm CMOS Process Technology  
Up to 132 User-Programmable I/O Pins  
Features  
250 MHz Internal Performance, Low-Power Antifuse  
FPGA  
Deterministic Timing  
Advanced Small-Footprint Packages  
Pin-to-Pin Compatibility with eX Commercial- and  
Industrial-Grade Devices  
Hot-Swap Compliant I/Os  
Single-Chip Solution  
Nonvolatile  
Live on Power-Up  
Unique In-System Diagnostic and Verification  
Capability with Silicon Explorer II  
Boundary Scan Testing in Compliance with IEEE  
Standard 1149.1 (JTAG)  
FuseLock™ Secure Programming Technology  
Prevents Reverse Engineering and Design Theft  
Product Profile  
Device  
eX64  
eX128  
eX256  
Capacity  
3,000  
2,000  
6,000  
4,000  
12,000  
8,000  
System Gates  
Typical Gates  
Register Cells  
Dedicated Flip-Flops  
Maximum Flip-Flops  
64  
128  
128  
256  
256  
512  
Combinatorial Cells  
Maximum User I/Os  
128  
84  
256  
100  
512  
132  
Global Clocks  
Hardwired  
Routed  
1
2
1
2
1
2
Speed Grades*  
Std.  
A
Std.  
A
Std.  
A
Temperature Grades*  
Package (by pin count)  
TQFP  
CSP  
64, 100  
49, 128  
64, 100  
49, 128  
100  
128, 180  
Note: * The eX family is also offered in commercial and industrial temperature grades with –F, –P, and Std. speed grades. Refer to the eX  
Family FPGAs datasheet for more details.  
June 2006  
i
© 2006 Actel Corporation  

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