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EVAL-ADF7021-VDB2Z PDF预览

EVAL-ADF7021-VDB2Z

更新时间: 2022-12-16 16:06:45
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
60页 1552K
描述
HIgh Performance Narrow-Band Transceiver IC

EVAL-ADF7021-VDB2Z 数据手册

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ADF7021-V  
SPECIFICATIONS  
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25ꢀC. All  
measurements are performed with the EVAL-ADF7021-VDBxZ using the PN9 data sequence, unless otherwise noted. The version  
number of ETSI EN 300 200-1 is V2.3.1. LBW = loop bandwidth and IFBW = IF filter bandwidth.  
RF AND PLL SPECIFICATIONS  
Table 1.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
RF CHARACTERISTICS  
Phase Frequency Detector (PFD)  
Frequency  
RF/256  
24  
MHz  
Maximum usable PFD at a particular RF frequency  
is limited by the minimum N divider value  
PHASE-LOCKED LOOP (PLL)  
Normalized In-Band Phase Noise  
Floor1  
PLL Settling  
−203  
155  
dBc/Hz  
μs  
Measured for a 100 kHz frequency step to within  
5 ppm accuracy, PFD = 19.68 MHz, LBW = 8 kHz  
EXTERNAL VCO  
Tuning Range  
0.2  
0
2
V
dBm  
Pin L2 Input Sensitivity  
REFERENCE INPUT  
Crystal Reference2  
External Oscillator2, 3  
Crystal Start-Up Time4  
XTAL Bias = 20 μA  
XTAL Bias = 35 μA  
Input Level for External Oscillator  
OSC1 Pin  
VCO frequency < 1920 MHz  
3.625  
3.625  
24  
24  
MHz  
MHz  
10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V  
0.930  
0.438  
ms  
ms  
0.8  
V p-p  
V
Clipped sine wave  
OSC2 Pin  
CMOS levels  
ADC PARAMETERS  
Integral Nonlinearity (INL)  
Differential Nonlinearity (DNL)  
VDD = 2.3 V to 3.6 V, TA = 25°C  
0.4  
0.4  
LSB  
LSB  
1 This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance  
as seen at the power amplifier (PA) output: −203 + 10 log(fPFD) + 20 logN.  
2 Guaranteed by design. Sample tested to ensure compliance.  
3 A TCXO, VCXO, or OCXO can be used as an external oscillator.  
4 Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin.  
Rev. 0 | Page 4 of 60  
 
 

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