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EVAL-ADF4151EB1Z

更新时间: 2024-02-18 22:05:05
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亚德诺 - ADI /
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28页 450K
描述
Fractional-N/Integer-N PLL Synthesizer

EVAL-ADF4151EB1Z 数据手册

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Fractional-N/Integer-N PLL Synthesizer  
Data Sheet  
ADF4151  
FEATURES  
GENERAL DESCRIPTION  
Fractional-N synthesizer and integer-N synthesizer  
RF bandwidth to 3.5 GHz  
3.0 V to 3.6 V power supply  
The ADF4151 allows implementation of fractional-N or  
integer-N phase-locked loop (PLL) frequency synthesizers  
if used with an external voltage controlled oscillator (VCO),  
loop filter, and external reference frequency.  
1.8 V logic compatibility  
Separate charge pump supply (VP) allows extended tuning  
voltage (up to 5.5 V) in 3 V systems  
Programmable dual-modulus prescaler of 4/5 or 8/9  
Programmable RF output phase  
3-wire serial interface  
Analog and digital lock detect  
The ADF4151 is used with external VCO parts and is footprint  
and software compatible with the ADF4350. The part consists  
of a low noise digital phase frequency detector (PFD), a precision  
charge pump, and a programmable reference divider. There is  
a Σ-Δ based fractional interpolator to allow programmable  
fractional-N division. The INT, FRAC, and MOD registers  
define an overall N divider [N = (INT + (FRAC/MOD))]. The  
RF output phase is programmable for applications that require  
a particular phase relationship between the output and the  
reference. The ADF4151 also features cycle slip reduction  
circuitry, leading to faster lock times without the need for  
modifications to the loop filter.  
Switched bandwidth fast lock mode  
Cycle slip reduction  
APPLICATIONS  
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM,  
PCS, DCS, DECT)  
Test equipment  
Wireless LANs, CATV equipment  
Clock generation  
Control of all the on-chip registers is through a simple 3-wire  
interface. The device operates with a power supply ranging  
from 3.0 V to 3.6 V that can be powered down when not in use.  
The ADF4151 is available in a 5 mm × 5 mm package.  
FUNCTIONAL BLOCK DIAGRAM  
SDV  
AV  
x
DV  
V
R
SET  
DD  
DD  
DD  
P
MULTIPLEXER  
MUXOUT  
10-BIT R  
COUNTER  
÷2  
DIVIDER  
×2  
REF  
IN  
DOUBLER  
LOCK  
DETECT  
SW  
LD  
FL SWITCH  
O
CLK  
DATA  
LE  
DATA REGISTER  
FUNCTION  
LATCH  
CHARGE  
PUMP  
CP  
OUT  
PHASE  
COMPARATOR  
INTEGER  
REG  
FRACTION  
REG  
MODULUS  
REG  
THIRD-ORDER  
FRACTIONAL  
INTERPOLATOR  
RF  
RF  
+
IN  
N COUNTER  
IN  
ADF4151  
CE  
A
CP  
SD  
GND  
D
GND  
GND  
GND  
Figure 1.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2011 Analog Devices, Inc. All rights reserved.  
 
 
 
 

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