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EP3C5F256I8N PDF预览

EP3C5F256I8N

更新时间: 2024-01-16 14:24:10
品牌 Logo 应用领域
英特尔 - INTEL 可编程逻辑
页数 文件大小 规格书
10页 235K
描述
Field Programmable Gate Array, 5136-Cell, CMOS, PBGA256, 17 X 17 MM, 1.55 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-256

EP3C5F256I8N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred包装说明:LBGA, BGA256,16X16,40
Reach Compliance Code:compliant风险等级:5.8
JESD-30 代码:S-PBGA-B256JESD-609代码:e1
长度:17 mm湿度敏感等级:3
输入次数:182逻辑单元数量:5136
输出次数:182端子数量:256
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA256,16X16,40封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE峰值回流温度(摄氏度):260
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:1.55 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.25 V最小供电电压:1.15 V
标称供电电压:1.2 V表面贴装:YES
技术:CMOS端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:17 mmBase Number Matches:1

EP3C5F256I8N 数据手册

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1. Cyclone III Device Family Overview  
CIII51001-1.1  
The Cyclone® III FPGA family offered by Altera is a cost-optimized, memory-rich FPGA family.  
Cyclone III FPGAs are built on TSMC's 65-nm low-power (LP) process technology with additional  
silicon optimizations and software features to minimize power consumption. With this third  
generation in the Cyclone series, Altera broadens the number of high volume, cost-sensitive  
applications that can benefit from FPGAs.  
Cyclone III:  
Lowest  
System-Cost  
FPGAs  
This chapter contains the following sections:  
“Cyclone III Device Features” on page 1–1  
“Cyclone III Device Architecture” on page 1–4  
“Reference and Ordering Information” on page 1–9  
“Reference and Ordering Information” on page 1–9  
Cyclone III devices are designed to offer low-power consumption and increased system integration  
at reduced cost.  
Cyclone III  
Device Features  
Reduced Cost  
Cyclone III devices deliver the lowest device and system costs based on the following facts:  
Staggered I/O ring to lower die area  
Wide range of low cost packages  
Support for low-cost serial flash and commodity parallel flash devices for configuration  
Lowest-Power 65-nm FPGA  
Cyclone III devices are the lowest-power 65-nm FPGAs designed via TSMC’s 65-nm low power  
process and Altera’s power aware design flow. Cyclone III devices support hot-socketing operation;  
therefore, unused I/O banks can be powered down when the devices to which they are connected are  
turned off. Benefits of the Cyclone III device's low-power operation include:  
Extended battery life for portable and handheld applications  
Enabled operation in thermally challenged environments  
Eliminated or reduced cooling system costs  
Increased System Integration  
Cyclone III devices provide increased system integration by offering the following features:  
Density is up to 119,088 logic elements (LEs) and memory is up to 3.8 Mbits. Refer to Table 1–1  
on page 1–2.  
High memory to logic ratio for embedded DSP applications  
Highest multiplier-to-logic ratio in the industry at every density; 260 MHz multiplier  
performance  
High I/O count, low- and mid-range density devices for user I/O constrained applications  
Up to four phase-locked loops (PLLs) provide robust clock management and synthesis for device  
clocks, external system clocks, and I/O interfaces  
Up to five outputs per PLL  
Cascadable to save I/Os, ease PCB routing, and reduce the number of external reference  
clocks needed  
Dynamically reconfigurable to change phase shift, frequency multiplication/division, and  
input frequency in-system without reconfiguring the device  
Altera Corporation  
July 2007  
1–1  
Preliminary  

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